vivado综合hls类ip核报错问题解决方案

报错描述 moudle “” not found 等，每个ip核3行

解决方法1：路径过长，缩减路径

解决方法2：将系统时间改至2018年之前后编译

解决方法3：https://support.xilinx.com/s/article/70400?language=en_US待验证（可能无效暂不清楚原因） 内容如下

This issue is due to a difference between Project and Non-project mode and how HLS based IP are handled.

The generate_target command will usually take care of creating all of the HDL files needed for synthesis.

However, for design that contain an HLS IP core (V_tpg in the example above), the flow requires the compile_c command to be run in order to generate the needed HDL from the C code that is delivered during generation. 

In project mode, the compile_c command is run automatically but in non-project mode a user will need to insert it between target generation and synthesis.

For example:

read_bd <BD_NAME>.bd
set_property synth_checkpoint_mode None [get_files <BD_NAME>.bd]
generate_target -force all [get_files <BD_NAME>.bd]
compile_c [get_ips design_1_v_tpg_0]
synth_design
To automatically detect which, if any, IP cores in the project are HLS IP and run compile_c on this IP cores, you can run the following command line:

foreach ip_in_proj [get_ips] {if {[lsearch [get_property KNOWN_TARGETS [get_ipdefs [get_property ipdef [get_ips $ip_in_proj\\]]\\]] synthesis_c_source]>=1} {compile_c [get_ips $ip_in_proj}}
If you are unsure which, if any, IP cores in the project are HLS based, you can also just run compile_c on all of the IP (foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj}).

If the command is run on a non-HLS IP core, the command will ignore that IP core.

To detect which IP in the Xilinx install are HLS IP, run the following command:

foreach ip [get_ipdefs] {if {[lsearch [get_property KNOWN_TARGETS [get_ipdefs $ip\\]] synthesis_c_source]>=1} {puts $ip}}
For example: In Vivado 2017.4, the following IP VLNV will be returned.

xilinx.com:ip:v_gamma_lut:1.0
xilinx.com:ip:v_frmbuf_wr:2.0
xilinx.com:ip:v_demosaic:1.0
xilinx.com:ip:v_frmbuf_rd:2.0
xilinx.com:ip:v_mix:2.0
xilinx.com:ip:v_tpg:7.0