更新
2021-12-23_v1
更新TCL全流程代码,增加参数传递的功能。
增加参考文献6。
前言
之前都在用gui,后来项目要求用tcl脚本。网上的教程大都不涉及IP和block design。所以把自己的脚本放上来。
脚本适用于已经有GUI的工程,然后想转TCL模式。
测试环境
系统:Windows 10 专业版 64位
版本号:21H1
Vivado版本:2020.2
从现有工程得到IP和BlockDesign的TCL脚本
- 打开现有工程。
- 生成IP tcl
write_ip_tcl -force [get_ips] create_ip.tcl
- 生成BlockDesign tcl
open_bd_design bd_design_name
write_bd_tcl -force create_bd.tcl
最初的TCL 全流程代码
简要的说明
- E:/JTAG_BRAM_TCL 是工程运行目录, 根据需要修改
- src_dir 是源文件所在目录
- xdc_dir 是约束文件所在目录
- output_dir 是所有生成的报告和位流所在的目录
代码
cd E:/JTAG_BRAM_TCL
file delete -force .gen
file delete -force .srcs
file delete -force .Xil
# 0 basic config
## 0.1 set dir
set src_dir "E:/JTAG_BRAM/project_JTAG_BRAM/project_JTAG_BRAM.srcs/sources_1/new"
set xdc_dir "E:/JTAG_BRAM/project_JTAG_BRAM/project_JTAG_BRAM.srcs/constrs_1/new"
set output_dir "output_dir"
file mkdir $output_dir
## 0.2 set design parameter
set top_design_name "top"
set target_part "xcvu9p-flga2104-2L-e"
set target_board_part "xilinx.com:vcu118:part0:2.4"
set ip_name "blk_mem_gen_0"
set bd_name "design_1"
set ip_xci_path .srcs/sources_1/ip/$ip_name/$ip_name.xci
set bd_path .srcs/sources_1/bd/$bd_name/$bd_name.bd
set bd_wrapper_path .gen/sources_1/bd/$bd_name/hdl/${bd_name}_wrapper.v
set_part $target_part
set_property TARGET_LANGUAGE "Verilog" [current_project]
set_property BOARD_PART $target_board_part [current_project]
set_property DEFAULT_LIB work [current_project]
# 1 read source file
# 1.1 read_ip
source create_ip.tcl
read_ip $ip_xci_path
generate_target all [get_ips $ip_name]
synth_ip [get_ips $ip_name]
add_files $ip_xci_path
# 1.2 read block design
source create_bd.tcl
read_bd $bd_path
open_bd_design $bd_path
make_wrapper -files [get_files $bd_path] -top
read_verilog $bd_wrapper_path
set_property synth_checkpoint_mode None [get_files $bd_path]
generate_target all [get_files $bd_path]
# 1.3 read
read_verilog $src_dir/top.v
read_xdc $xdc_dir/top.xdc
# 2 run synthesis, report utilization and timing estimates, write checkpoint design
synth_design -top $top_design_name -part $target_part
write_checkpoint -force $output_dir/post_synth
report_timing_summary -file $output_dir/post_synth_timing_summary.rpt
report_power -file $output_dir/post_synth_power.rpt
# 3 run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
opt_design
place_design
phys_opt_design
write_checkpoint -force $output_dir/post_place
report_timing_summary -file $output_dir/post_place_timing_summary.rpt
#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
route_design
write_checkpoint -force $output_dir/post_route
report_timing_summary -file $output_dir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $output_dir/post_route_timing.rpt
report_clock_utilization -file $output_dir/clock_util.rpt
report_utilization -file $output_dir/post_route_util.rpt
report_power -file $output_dir/post_route_power.rpt
report_drc -file $output_dir/post_imp_drc.rpt
write_verilog -force $output_dir/${top_design_name}_impl_netlist.v
write_xdc -no_fixed_only -force $output_dir/${top_design_name}_impl.xdc
#5: generate a bitstream
write_bitstream -force $output_dir/${top_design_name}.bit
write_debug_probes -force $output_dir/${top_design_name}.ltx
2021-12-23_v1更新后TCL 全流程代码
参数传递用到一些函数的说明:$argc 表示参数的个数,$argv 表示参数列表。lindex $argv 0 表示取出 参数列表里面第一个参数
#cd /net/dellr740b/home/soc/fengbh/work/soc_fpga_v1_13
# file delete -force output_dir
# get args
if { $argc != 2 } {
puts "The script requires two argv to be input."
puts "For example, vivado -mode batch -source fpga_no_project.tcl <soc_dir> <src_tcl>".
puts "Please try again."
} else {
puts [lindex $argv 0]
puts [lindex $argv 1]
}
##############################################################
file delete -force .gen
file delete -force .srcs
file delete -force .Xil
# 0 basic config
## 0.1 set dir
set project_dir "."
set soc_dir [lindex $argv 0]
set src_tcl [lindex $argv 1]
set src_dir ${soc_dir}/modules_fpga/scripts/src_dir
set python_dir ${soc_dir}/modules_fpga/scripts/python_dir
set output_dir ${project_dir}/output_dir
file mkdir $project_dir
file mkdir $output_dir
## 0.2 set design parameter
set top_design_name "chip_fpga_top"
set target_part "xcvu9p-flga2104-2L-e"
set target_board_part "xilinx.com:vcu118:part0:2.0"
set bram_ip_name "blk_mem_gen_0"
set clk_ip_name "clk_wiz_0"
set bd_1_name "design_1"
set bd_2_name "design_2"
set bram_ip_xci_path ${project_dir}/.srcs/sources_1/ip/$bram_ip_name/$bram_ip_name.xci
set clk_ip_xci_path ${project_dir}/.srcs/sources_1/ip/$clk_ip_name/$clk_ip_name.xci
set bd_1_path ${project_dir}/.srcs/sources_1/bd/$bd_1_name/$bd_1_name.bd
set bd_2_path ${project_dir}/.srcs/sources_1/bd/$bd_2_name/$bd_2_name.bd
set bd_1_wrapper_path ${project_dir}/.srcs/sources_1/bd/$bd_1_name/hdl/${bd_1_name}_wrapper.v
set bd_2_wrapper_path ${project_dir}/.srcs/sources_1/bd/$bd_2_name/hdl/${bd_2_name}_wrapper.v
set_part $target_part
set_property TARGET_LANGUAGE "Verilog" [current_project]
set_property BOARD_PART $target_board_part [current_project]
set_property DEFAULT_LIB work [current_project]
# 1 read source file
# 1.1 read_ip
source $src_dir/create_ip.tcl
read_ip $bram_ip_xci_path
read_ip $clk_ip_xci_path
generate_target all [get_ips $bram_ip_name]
generate_target all [get_ips $clk_ip_name]
synth_ip [get_ips $bram_ip_name]
synth_ip [get_ips $clk_ip_name]
add_files $bram_ip_xci_path
add_files $clk_ip_xci_path
# 1.2 read block design
source $src_dir/create_bd_1.tcl
read_bd $bd_1_path
open_bd_design $bd_1_path
make_wrapper -files [get_files $bd_1_path] -top
read_verilog $bd_1_wrapper_path
set_property synth_checkpoint_mode None [get_files $bd_1_path]
generate_target all [get_files $bd_1_path]
source $src_dir/create_bd_2.tcl
read_bd $bd_2_path
open_bd_design $bd_2_path
make_wrapper -files [get_files $bd_2_path] -top
read_verilog $bd_2_wrapper_path
set_property synth_checkpoint_mode None [get_files $bd_2_path]
generate_target all [get_files $bd_2_path]
# 1.2 read
source ${python_dir}/output/fpga_stub.tcl
read_xdc $src_dir/top.xdc
#read_xdc $src_dir/top_timing.xdc
# 2 run synthesis, report utilization and timing estimates, write checkpoint design
synth_design -top $top_design_name -part $target_part -gated_clock_conversion on -retiming
write_checkpoint -force $output_dir/post_synth
report_timing_summary -file $output_dir/post_synth_timing_summary.rpt
report_power -file $output_dir/post_synth_power.rpt
# 3 run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
opt_design
place_design -directive ExtraTimingOpt
phys_opt_design -directive ExploreWithHoldFix
write_checkpoint -force $output_dir/post_place
report_timing_summary -file $output_dir/post_place_timing_summary.rpt
#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
route_design -directive NoTimingRelaxation
write_checkpoint -force $output_dir/post_route
report_timing_summary -file $output_dir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $output_dir/post_route_timing.rpt
report_clock_utilization -file $output_dir/clock_util.rpt
report_utilization -file $output_dir/post_route_util.rpt
report_power -file $output_dir/post_route_power.rpt
report_drc -file $output_dir/post_imp_drc.rpt
write_verilog -force $output_dir/${top_design_name}_impl_netlist.v
write_xdc -no_fixed_only -force $output_dir/${top_design_name}_impl.xdc
#5: generate a bitstream
write_bitstream -force $output_dir/${top_design_name}.bit
write_debug_probes -force $output_dir/${top_design_name}.ltx
参考文档
- UG 892-Vivado Design Suite UserGuideDesign Flows Overview
- UG 894-Vivado Design Suite UserGuideUsing Tcl Scripting
- UG 835-Vivado Design Suite TclCommand Reference Guide
- UG 896-Vivado Design Suite User GuideDesigning with IP
- UG 994-Vivado Design Suite UserGuideDesigning IP Subsystems Using IPIntegrator
- Vivado - 如何在 Vivado 命令行模式下将 argv/argc 传递给 TCL?