各厂商综合工具,对HDL综合时都定义了一些综合属性这些属性可指定a declaration,a module item,a statement, or a port connection 不同的综合方式。
语法为:
/* synthesis, <any_company_specific_attribute = value_or_optional_value */
下面就是Altera的几个常用的Synthesis attributes
Noprune
A Verilog HDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.
一种Verilog HDL综合属性,防止Quartus II软件删除不直接或间接为顶级输出或bidir管脚供电的寄存器。
For example:
reg reg1 /* synthesis noprune */;
keep
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular net when optimizing combinational logic.
一种Verilog HDL综合属性,指导分析与综合在优化组合逻辑时不最小化或删除特定网络。
For example:
wire keep_wire /* synthesis keep */;
preserve
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.
一种Verilog HDL综合属性,当消除冗余寄存器或具有恒定驱动器的寄存器时,它指导分析与综合不最小化或删除特定寄存器。
For example:
reg reg1 /* synthesis preserve */;
ram_init_file
A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory.
Verilog HDL合成属性,指定推断内存的初始内容。
For example:
reg [7:0] mem[0:255] /* synthesis ram_init_file = " my_init_file.mif" */;
ramstyle
A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM.
M512", "M4K", "M9K", "M144K", "MLAB", "M-RAM”
Verilog HDL合成属性,指定在实现推断的RAM时要使用的TriMatrix内存块的类型。
For example:
reg [0:7] my_ram[0:63] /* synthesis ramstyle = "M512" */;
translate_off or translate_on
Verilog HDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.
Verilog HDL综合指令,直接分析和综合,忽略特定于仿真和逻辑综合无关的部分设计代码。
For example:
parameter tpd = 2; // Generic delays
// synthesis translate_off
#tpd;
// synthesis translate_on
关于状态机有下面三个综合属性:
full_case
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to treat unspecified state values in a Verilog Design File Case Statement as don't care values, and therefore to treat the Case Statement as "full".
仅用于Verilog ,与case 语句一起使用表明所有可能的状态都已经给出不需要其他逻辑保持信号的值.
module full_case (a, sel, y);
input [3:0] a;
input [1:0] sel;
output y;
reg y;
always @(a or sel) case (sel) // synthesis full_case
2'b00: y="a"[0];
2'b01: y="a"[1];
2'b10: y="a"[2];
endcase
endmodule
parallel_case
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File Case Statement.
仅用于Verilog ,与case 语句一起使用强制生成一个并行的多路选择结构而不是一个优
先译码结构.
module parallel_case (sel, a, b, c);
input [2:0] sel;
output a, b, c;
reg a, b, c;
always @(sel) begin
{a, b, c} = 3'b0;
casez (sel) // synthesis parallel_case
3'b1??: a = 1'b1;
3'b?1?: b = 1'b1;
3'b??1: c = 1'b1;
endcase
end
endmodule
syn_encoding
A Verilog HDL synthesis attribute that determines how the Quartus II software should encode the states of an inferred state machine.
强制重新状态机的状态编码方式.有default,one-hot,sequential,gray,johnson,compact,user几种编码方式
(* syn_encoding = "user" *) reg [1:0] state;
parameter init = 0, last = 3, next = 1, later = 2;
always @ (state) begin
case (state)
init:
out = 2'b01;
next:
out = 2'b10;
later:
out = 2'b11;
last:
out = 2'b00;
endcase
end
In the above example, the states will be encoded as follows:
init = "00"
last = "11"
next = "01"
later = "10"
文章参考:https://www.cnblogs.com/shengansong/archive/2011/12/18/2291531.html