[HDLbits] Count clock（12小时制时钟问题）

易错点：am到pm的变化

11:00am --> 12:00pm
11:00pm --> 12:00am

verilog代码

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    wire h_reset;
    wire [2:0] enable;
    assign enable[0] = ena;
    assign enable[1] = (ss == 8'b0101_1001);
    assign enable[2] = (mm == 8'b0101_1001)&&(ss == 8'b0101_1001);
    

    
    my_bcd my_bcd0(clk, reset, enable[0], ss);		//1s -> 60s(1min)
    my_bcd my_bcd1(clk, reset, enable[1], mm);		//1min -> 60min(1h)
    my_bcd_hh my_bcd2(clk, reset , enable[2], hh, pm);		//1h -> 12h
    
endmodule

module my_bcd(
	input clk,
    input reset,
    input enable,
    output reg [7:0] q
  
);
    
    always @(posedge clk)begin
        if(reset || ((q == 8'b0101_1001)&&enable))
            q <= 8'b00000000;
        else if(enable && (q[3:0]!=4'b1001))
            q <= q + 4'b1;
        else if(enable && (q[3:0]==4'b1001))begin
            q[7:4] <= q[7:4] + 4'b1;
            q[3:0] <= 4'b0;
        end
    end
            
            
    
    
endmodule

module my_bcd_hh(
	input clk,
    input reset,
    input enable,
    output reg  [7:0]  q,
    output reg pm
  
);
    
    
    always @(posedge clk)begin
        if(reset)begin
            q <= 8'b0001_0010;			//12 am 
        	pm <= 1'b0;
        end
        else if(enable && (q == 8'b0001_0010))begin		//12 --> 1
            q <= 8'b0000_0001;
        end
        else if(enable && (q == 8'b0001_0001) &&(pm == 1'b1))begin		//11pm --> 12am
            q <= 8'b0001_0010;
            pm <= 1'b0;
        end
        else if(enable && (q == 8'b0001_0001) &&(pm == 1'b0))begin		//11am --> 12pm
            q <= 8'b0001_0010;
            pm <= 1'b1;
        end
        else if(enable && (q[3:0]!=4'b1001))
            q <= q + 4'b1;
        else if(enable && (q[3:0]==4'b1001))begin
            q[7:4] <= q[7:4] + 4'b1;
            q[3:0] <= 4'b0;
        end
    end
  
endmodule

tb激励文件

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/01/30 13:35:00
// Design Name: 
// Module Name: module_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//

module module_tb(

//输入
	reg clk; 
	reg rst_n; 
	reg ena;
//输出
  wire  [7:0] hh;
  wire  [7:0] mm;
  wire  [7:0] ss;
  wire pm;

//信号初始化
initial begin
	clk = 1'b0;
	rst_n = 1'b1;
	ena = 1'b0;
	#100 rst_n = 1'b0;//延时100ns开始启动
	#100 ena = 1'b1;//延时100ns开始启动
end

//生成时钟，模拟晶振实际的周期时序
always #10 clk = ~clk; //每10ns，sys_clk进行翻转，达到模拟晶振周期为20ns
//或者：forever clk = #10 ~clk;

//模块例化
top_module top_module_tb(
    .clk(clk),
    .reset(rst_n),
    .ena(ena),
    . pm(pm),
    . hh(hh),
    . mm(mm),
    . ss(ss)
    ); 

endmodule