![](https://img-blog.csdnimg.cn/fd474689b06c4cc284f40c7f39c747ff.png?x-oss-process=image/resize,m_fixed,h_224,w_224)
HDLBits---Basic
Verilog Language Basic的答案汇总
材料狗转行ing
这个作者很懒,什么都没留下…
展开
-
08-Module Declaration
Verilog HDL(HDLBits)Verilog Language Basic08-Module Declarationmodule top_module ( input p1a, p1b, p1c, p1d, p1e, p1f, output p1y, input p2a, p2b, p2c, p2d, output p2y ); /*自己写的太冗余 wire temp_2ab,temp_2cd,temp_2abcd; //lef原创 2022-01-25 21:46:38 · 353 阅读 · 0 评论 -
06-Xnorgate
Verilog HDL(HDLBits)Verilog Language Basic06-Xnorgatemodule top_module( input a, input b, output out ); assign out = ~(a^b); endmodule原创 2022-01-25 20:56:38 · 185 阅读 · 0 评论 -
07-Declaring wires
Verilog HDL(HDLBits)Verilog Language Basic07-Declaring wires`default_nettype nonemodule top_module( input a, input b, input c, input d, output out, output out_n ); wire temp_1; wire temp_2; wire temp_3;原创 2022-01-25 20:54:10 · 105 阅读 · 0 评论 -
05-Norgate
Verilog HDL(HDLBits)Verilog Language Basic05-Norgatemodule top_module( input a, input b, output out ); assign out = ~(a|b); endmodule原创 2022-01-25 20:24:20 · 130 阅读 · 0 评论 -
04-Andgate
Verilog HDL(HDLBits)Verilog Language Basic03-Notgatemodule top_module( input a, input b, output out ); assign out = a&b; endmodule原创 2022-01-25 20:19:08 · 67 阅读 · 0 评论 -
03-Notgate
Verilog HDL(HDLBits)Verilog Language Basic03-Notgatemodule top_module( input in, output out ); assign out = ~in;endmodule原创 2022-01-25 20:04:06 · 70 阅读 · 0 评论 -
01-Wire
在一条线上实现输入到输出,赋值是“连续的”,因为即使右边的值发生变化,分配也一直在继续。连续作业不是一次性事件.原创 2022-01-25 19:54:34 · 70 阅读 · 0 评论 -
02-Wire4
Verilog练习日记原创 2022-01-25 19:38:45 · 75 阅读 · 0 评论