【GAOPS035】verilog打拍同步模板

目录

sync.v

tb.v

---

避免每次写,提高复用率。

上升下降沿只在单bit生效

sync.v

`timescale 1 ns / 100 ps
module sync #(
parameter WIDTH			=	4,
parameter DEPTH			=	4)
(
    input        				clk,
    input        				rst_n,
	
    input        [WIDTH-1:0]  	in_data,
    output       [WIDTH-1:0]  	out_data,
    output                  	out_n1p,//只在宽度是1生效，其他默认是0
    output                  	out_1p//只在宽度是1生效，其他默认是0
);
	genvar i;
	reg [WIDTH-1:0]  	data_reg [DEPTH-1:0] ;
	//第1个数
	always@(posedge clk or negedge rst_n)begin
		if(rst_n == 1'b0)begin
			data_reg[0] <= #1 {WIDTH{1'b0}};
		end  begin 
			data_reg[0] <= #1 in_data;
		end		
	end
	//第2个数以及以后
	generate for(i=1;i<DEPTH;i=1+i)begin :pipe
		always@(posedge clk or negedge rst_n)begin
			if(rst_n == 1'b0)begin
				data_reg[i] <= #1 {WIDTH{1'b0}};
			end else begin 
				data_reg[i] <= #1 data_reg[i-1];
			end		
		end
		end
	endgenerate	
	
	assign out_data = data_reg[DEPTH-1];
	
	generate 
	if(WIDTH == 1) begin 
		if(DEPTH == 0) begin 
		assign	out_n1p = 1'b0;
		assign	out_1p  = 1'b0;
		end else if(DEPTH == 1) begin 
		assign	out_n1p = (data_reg[0] & ~in_data)?1'b1:1'b0;
		assign	out_1p  = (~data_reg[0] & in_data)?1'b1:1'b0;
		end else begin
		assign	out_n1p = (data_reg[DEPTH-1] & ~data_reg[DEPTH-2])?1'b1:1'b0;
		assign	out_1p  = (~data_reg[DEPTH-1] & data_reg[DEPTH-2])?1'b1:1'b0;			
		end
	end	else begin 
		assign	out_n1p = 1'b0;
		assign	out_1p  = 1'b0;
	end
	endgenerate
	
	
endmodule

tb.v

`timescale 1 ns / 100 ps
module tb();
	reg clk=0,rst_n=0;	
	reg[31:0]rand1;
	always clk = #5 ~clk;
	always @(posedge clk) rand1 <= #1 {$random} % 100;	
	//复位
    initial begin
		rst_n = 1'b0;
		#30;
		rst_n = 1'b1;
    end
		
	sync #(.WIDTH(1),.DEPTH(2) ) u0(
		.clk		(clk  ),
		.rst_n		(rst_n),
		.in_data	(rand1),
		.out_n1p	( ),
		.out_1p	    ( ),
		.out_data	( )
		);
endmodule