verilog按位异或

Verilog输出数组的异或结果

题目要求
Build a combinational circuit with four inputs, in[3:0].
There are 3 outputs:
out_and: output of a 4-input AND gate.
out_or: output of a 4-input OR gate.
out_xor: output of a 4-input XOR gate.

答案
assign out_and=in[3]&in[2]&in[1]&in[0]; assign out_or=in[3]|in[2]|in[1]|in[0]; assign out_xor=^in;

原理
数组之间依次运行异或运算，如下所示
0001 0001
0001 0111
—————
0000 0110

练习
nums 为 [0, 2, 4, 6, 8] 按位异或结果为 8