module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
//内部信号
wire q1;
wire [15:0] sum1,sum2;
wire [31:0] b1;
//先把少数位数的值进行扩展,然后在进行按位进行异或
assign b1 = ((b & (~{32{sub}})) | ((~b) & {32{sub}}));
add16 instance1(
.a(a[15:0]),
.b(b1[15:0]),
.cin(sub),
.sum(sum1),
.cout(q1)
);
add16 instance2(
.a(a[31:16]),
.b(b1[31:16]),
.cin(q1),
.sum(sum2),
.cout()
);
assign sum = {sum2,sum1};
endmodule