有3种方法
1 :
Set the include.v file as global included and set its file_type to "Verilog Header".
If file_type is not set to Verilog Header, the include file will be treated as an ordinary Verilog file which can be referred by the other Verilog files and this causes the error above.
set_property file_type "Verilog Header" [get_files ../source_inclu/include.v]
set_property is_global_include true [get_files ../source_inclu/include.v]
2 :
Do not add the include.v file into project sources or read the include file in non-project mode.
Set the include_dirs option to the location of the include.v file in the synth_design command or Synthesis settings.
synth_design -top top -part xc7k70tfbg484-2 -include_dirs {../source_inclu}
参考数据手册:Xilinx Answer 54006
3 软件GUI 设置: