verilog实现序列检测（mealy型和moore型）

1、要求
实现序列检测，检测到1101，有效信号data_valid为1，否则为0.
2、实现代码：
（1）moore型
输出只和输入有关系

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/06/02 19:47:19
// Design Name: 
// Module Name: moore_sequence_check
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


//采用moore型状态描述
module moore_sequence_check(
input clk,
input rst_n,
input data_in,
output reg data_valid
);
reg [4:0]current_state;
reg [4:0]next_state;
parameter s0_idle=5'b00001,
		  s1=5'b00010,//1
		  s2=5'b00100,//11
		  s3=5'b01000,//110
		  s4=5'b10000;//1101
//第一个always：判断状态跳转，同步时序
always@(posedge clk )
if(!rst_n)
	current_state<=s0_idle;
else current_state<=next_state;
//第二个always，判断状态转移条件，组合逻辑
always@(*)
	case(current_state)
		s0_idle:if(data_in==1)
					next_state=s1;
				else next_state=s0_idle;
		s1:if(data_in==1)
			next_state=s2;
			else next_state=s0_idle;
		s2:if(data_in==0)
			next_state=s3;
			else next_state=s2;
		s3:if(data_in==1)
			next_state=s4;
			else next_state=s0_idle;
		s4:if(data_in==1)
			next_state=s2;
			else next_state=s0_idle;
		default:next_state=s0_idle;
	endcase
//第三个always,状态输出，同步时序
always@(posedge clk )
if(!rst_n)
	data_valid<=0;
else 
	begin
		case(next_state)
		s4:data_valid<=1;
		default:data_valid<=0;
		endcase
	end
endmodule

（2）mealy型
输出不仅和输入有关系，还和状态有关系

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/06/02 19:48:25
// Design Name: 
// Module Name: mealy_sequence_check
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


//采用mealy型状态描述
module mealy_sequence_check(
input clk,
input rst_n,
input data_in,
output reg data_valid
);
reg [4:0]current_state;
reg [4:0]next_state;
parameter s0_idle=5'b0001,
		  s1=5'b0010,//1
		  s2=5'b0100,//11
		  s3=5'b1000;//110
		 
//第一个always：判断状态跳转，同步时序
always@(posedge clk )
if(!rst_n)
	current_state<=s0_idle;
else current_state<=next_state;
//第二个always，判断状态转移条件，组合逻辑
always@(*)
	case(current_state)
		s0_idle:if(data_in==1)
					next_state=s1;
				else next_state=s0_idle;
		s1:if(data_in==1)
			next_state=s2;
			else next_state=s0_idle;
		s2:if(data_in==0)
			next_state=s3;
			else next_state=s2;
		s3:if(data_in==1)
			next_state=s1;
			else next_state=s0_idle;
		
		default:next_state=s0_idle;
	endcase
//第三个always,状态输出，同步时序
always@(posedge clk )
if(!rst_n)
	data_valid<=0;
else 
	begin
		case(next_state)
		s3:if(data_in==1)data_valid<=1;else data_valid<=0;
		default:data_valid<=0;
		endcase
	end
endmodule

（3）状态图

由上可得mealy型比moore型少一个状态。