Alwaysblock2

For hardware synthesis, there are two types of always blocks that are relevant:

• Combinational: always @(*)
• Clocked: always @(posedge clk)

Clocked always blocks create a blob of combinational logic just like combinational always blocks, but also creates a set of flip-flops (or "registers") at the output of the blob of combinational logic. Instead of the outputs of the blob of logic being visible immediately, the outputs are visible only immediately after the next (posedge clk).

Blocking vs. Non-Blocking Assignment

There are three types of assignments in Verilog:

• Continuous assignments (assign x = y;). Can only be used when not inside a procedure ("always block").
• Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
• Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.

In a combinational always block, use blocking assignments. In a clocked always block, use non-blocking assignments. A full understanding of why is not particularly useful for hardware design and requires a good understanding of how Verilog simulators keep track of events. Not following this rule results in extremely hard to find errors that are both non-deterministic and differ between simulation and synthesized hardware.

对于硬件合成，有两种类型的始终块是相关的：组合：总是@（*）
时钟：始终@（posedge clk）
时钟始终块创建了一个组合逻辑块，就像组合始终块一样，但也在组合逻辑块的输出端创建了一组触发器（或“寄存器”）。逻辑块的输出不是立即可见的，而是仅在下一个逻辑块之后立即可见的（posedge clk）。

阻塞与非阻塞分配
Verilog中有三种类型的赋值：

连续作业（分配x=y；）。只能在不在过程内部时使用（“始终阻塞”）。
程序阻塞赋值：（x=y；）。只能在程序内部使用。
程序性非阻塞赋值：（x<=y；）。只能在程序内部使用。
在组合始终块中，使用块分配。在时钟总是块中，使用非块分配。充分理解为什么对硬件设计不是特别有用，需要很好地理解Verilog模拟器如何跟踪事件。不遵循此规则会导致极难发现的错误，这些错误既不确定，又在模拟和合成硬件之间有所不同。

Build an XOR gate three ways, using an assign statement, a combinational always block, and a clocked always block. Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed.

使用赋值语句、组合始终块和时钟始终块三种方式构建XOR门。请注意，时钟始终块产生的电路与其他两个不同：有一个触发器，因此输出延迟。

// synthesis verilog_input_version verilog_2001
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    
    assign out_assign = a^b;
    always @(*)begin
        out_always_comb = a^b;
    end
    always@(posedge clk)begin
        out_always_ff = a^b;
    end

endmodule