Always nolatches

Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.

假设你正在构建一个电路来处理游戏PS/2键盘的扫描码。给定接收到的扫描码的最后两个字节，您需要指示是否按下了键盘上的一个箭头键。这涉及一个相当简单的映射，它可以实现为一个包含四个案例的case语句（或if-elseif）。

Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.

To avoid creating latches, all outputs must be assigned a value in all possible conditions (See also always_if2). Simply having a default case is not enough. You must assign a value to all four outputs in all four cases and the default case. This can involve a lot of unnecessary typing. One easy way around this is to assign a "default value" to the outputs before the case statement:

您的电路有一个16位输入和四个输出。构建这个电路，识别这四个扫描码并断言正确的输出。

为了避免创建锁存器，必须在所有可能的情况下为所有输出分配一个值（另请参见always_if2）。仅仅有一个默认案例是不够的。在所有四种情况和默认情况下，您必须为所有四个输出分配一个值。这可能涉及大量不必要的打字。一个简单的方法是在case语句之前为输出分配一个“默认值”：

always @(*) begin
    up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
    case (scancode)
        ... // Set to 1 as necessary.
    endcase
end

This style of code ensures the outputs are assigned a value (of 0) in all possible cases unless the case statement overrides the assignment. This also means that a default: case item becomes unnecessary.

Reminder: The logic synthesizer generates a combinational circuit that behaves equivalently to what the code describes. Hardware does not "execute" the lines of code in sequence.

这种代码风格确保在所有可能的情况下为输出分配一个值（0），除非case语句覆盖了该分配。这也意味着默认值：case项变得不必要。

提醒：逻辑合成器生成一个组合电路，其行为与代码描述的行为等效。硬件不会按顺序“执行”代码行。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always @(*)begin
        up = 2'b0;down = 2'b0;left = 2'd0;right = 2'd0;
        case(scancode)
        	16'he06b : left  = 1;
            16'he072 : down =1;
            16'he074 : right =1;
            16'he075 : up =1;
            default ;
        
        
        endcase   
    end

endmodule

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always@(*)begin
        case(scancode) 
            16'he075: begin
                    down=0;
                    left=0;
                    right=0;
                    up=1;
                end
            16'he072: begin
                    down=1;
                    left=0;
                    right=0;
                    up=0;
                end
            16'he074:begin
                    down=0;
                    left=0;
                    right=1;
                    up=0;
                end
            16'he06b: begin
                    down=0;
                    left=1;
                    right=0;
                    up=0;
                end
            default: begin
                    down=0;
                    left=0;
                    right=0;
                    up=0;
                end
        endcase
        end
 
endmodule