Dualedge

  module top_module (
2      input clk,
3      input d,
4      output q
5  );
6      reg neg_q, pos_q;
7    
8      always@(negedge clk)//negedge triggered flip-flop
9          neg_q <= d; 
10     always@(posedge clk)//posedge triggered flip-flop
11         pos_q <= d;  
12      assign q = clk ? pos_q : neg_q;//a mux for out       
13    
14 endmodule