Moore状态机和Mealy状态机的区别(以序列检测器为例)

最新推荐文章于 2023-08-26 22:14:45 发布

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最新推荐文章于 2023-08-26 22:14:45 发布

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分类专栏： # Verilog基础文章标签：状态机 verilog fpga

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一、Moore状态机

输出只与此时的状态有关，因此假如需要检测宽度为4的序列，则需要五个状态。

设计一个序列检测器，检测序列1101，检测到输出1，否则输出0。

`timescale 1ns / 1ps
 
module seq_det_moore(
    input clk,
    input reset,
    input din,
    output reg dout
    );
    //状态声明
    localparam [2:0]
    s0 = 3'b000,
    s1 = 3'b001,
    s2 = 3'b010,
    s3 = 3'b011,
    s4 = 3'b100;
    
    reg [2:0] current_state,next_state;
    
    always @(posedge clk, posedge reset)
    begin
        if(reset)
            current_state <= s0;
        else
            current_state <= next_state;
    end
    
    always @ *
    begin
        case(current_state)
        s0:
            if(din == 1'b1) next_state = s1;
            else next_state = s0;
        s1:
            if(din == 1'b1) next_state = s2;
            else next_state = s0;
        s2:
            if(din == 1'b0) next_state = s3;
            else next_state = s2;
        s3:
            if(din == 1'b1) next_state = s4;
            else next_state = s0;
        s4:
            if(din == 1'b1) next_state = s1;
            else next_state = s0;
        default: next_state = s0;
        
        endcase
    
    end
    
    always @*
    begin
        if(current_state == s4) dout = 1;
        else dout = 0;
    end
    
    
endmodule

二、Mealy状态机

输出与此时的状态以及输入有关，因此假如需要检测宽度为4的序列，只需要四个状态即可。

设计一个序列检测器，检测序列1101，检测到输出1，否则输出0。

`timescale 1ns / 1ps

module seq_det_mealy(
    input clk,
    input reset,
    input din,
    output reg dout
    );
	
	localparam [1:0]
	s0 = 2'b00,
	s1 = 2'b01,
	s2 = 2'b10,
	s3 = 2'b11;
	
	reg [1:0] current_state,next_state;
	
	always @(posedge clk, posedge reset)
	begin
		if(reset)
			current_state <= s0;
		else
			current_state <= next_state;
	
	end
	
	always @ *
	begin
		case(current_state)
		s0:
			if(din == 1'b1) next_state = s1;
			else next_state = s0;
		s1: 
			if(din == 1'b1) next_state = s2;
			else next_state = s1;
		s2:
			if(din == 1'b0) next_state = s3;
			else next_state = s2;
		s3: next_state = s0;
		default: next_state = s0;
		endcase
	
	end
	
	always @ *
	begin
		if(reset) dout = 1'b0;
		else if( (current_state == s3)&&(din == 1'b1) ) dout = 1'b1;
		else dout = 1'b0;
	
	end
	
	
endmodule