HDLBits-12-hour clock

最新推荐文章于 2024-05-13 23:01:00 发布

郭学鑫

最新推荐文章于 2024-05-13 23:01:00 发布

阅读量823

点赞数

分类专栏： HDLBits 文章标签： fpga verilog

本文链接：https://blog.csdn.net/qq_40996256/article/details/118680531

版权

本文介绍如何使用Verilog设计一个12小时制的时钟，包括BCD计数器，AM/PM指示，以及复位和使能功能。在11:59:59 AM到12:00:00 PM之间展示了状态转换，并强调了复位优先级和计数器的特殊循环逻辑。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

题目：

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

题目理解：

总共需要用到6个BCD counter，表示时、分、秒各两个，时从01计到12，分从00计到59，秒从00计到59；复位时显示AM 12:00:00；复位的优先级高于enable，也就是说，即使enable为0，只要复位，也要显示AM 12:00:00。

正确代码：

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    reg [3:0] ss0,ss1,mm0,mm1,hh1,hh0;
    reg [3:0] state;
    
    always @ (posedge clk) begin
        if(reset)
            ss0 <= 4'd0;
        else if(ena) begin
            if(ss0 == 4'd9)
                ss0 <= 4'd0;
            else
                ss0 <= ss0 + 4'd1;
        end
        else
            ss0 <= ss0;
    end
    
    always @ (posedge clk) begin
        if(reset)
            ss1 <= 4'd0;
        else if(ss1 == 4&

最低0.47元/天解锁文章