题目:
Implement the following circuit:
正确代码:
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output reg out);
reg [2:0] q;
always @ (posedge clk) begin
if(!resetn) begin
q <= 3'd0;
out <= 1'b0;
end
else begin
q <= {in,q[2:1]};
out <= q[0];
end
end
endmodule
所犯错误:
q <= in >> 4;