module cy4(input T,
input clk,
input rst_n,
output reg Q
);
always @(posedge clk or negedge rst_n)
if(!rst_n) Q <= 1'b0;
else if(T == 1) Q <= ~Q;
else if(T == 0) Q <= Q;
else;
endmodule
测试脚本代码:
`timescale 1 ns/ 1 ps
module cy4_vlg_tst();
reg T;
reg clk;
reg rst_n;