FPGA Verilog 按键与LED组合设计

1. 用点亮4盏LED灯；
2. 4盏LED灯在1秒内轮流点亮，即每盏LED灯的点亮时间是250毫秒；
3. 一个轮流完成后，用一个4位的加法器累加LED循环的次数；
4. 即当每一轮第四盏LED熄灭后，将这四盏LED灯改为同时点亮，显示出加法器中的16进制的数值，点亮时间为2秒；
5. 加法器的数值从0~F循环

module key_test(clk,rst_n,light,key);
    input clk;
    input rst_n;
    input key;
    output reg[3:0] light;   //灯

reg [31:0] timer;
reg [3:0] adder = 4'b0000;
reg [19:0] cnt_20ms;
reg key_flag = 1'b0; 
reg adder_stop = 1'b1;
reg [31:0]timer_final;

parameter T_NORMAL = 32'd149_999_999;
parameter T_SKIP = 32'd49_999_999;
parameter CNT_MAX = 20'd999_999;

//消抖
always@(posedge clk or negedge rst_n)
begin
    if (rst_n == 1'b0)
        cnt_20ms <= 20'd0;
	else if( key == 1'b1 )
		cnt_20ms <= 20'd0;                             
	else if(cnt_20ms == CNT_MAX)
		cnt_20ms <= CNT_MAX;
	else
		cnt_20ms <= cnt_20ms + 20'd1;
end

always@(posedge clk or negedge rst_n)
begin
    if (rst_n == 1'b0)
        key_flag <= 1'b0;
	else if( cnt_20ms == (CNT_MAX -20'd1) )
		key_flag <= 1'b1;                             
	else 
		key_flag <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
    if (rst_n == 1'b0)
        adder_stop <= 1'b0;
	else if( key_flag == 1'b1 )
	begin 
	if(adder_stop == 1'b0 )
		adder_stop <= 1'b1;                             //stop adder
	else if(adder_stop == 1'b1 )
		adder_stop <= 1'b0;
	end
	else
		adder_stop <= adder_stop;
end


always@(posedge clk or negedge rst_n)
begin
    if (rst_n == 1'b0)
        timer <= 32'd0;
	else if (timer == T_NORMAL)
		timer <= 32'd0;
	else if ((adder_stop == 1'd1) && (timer == T_SKIP))
		timer <= 32'd0;
	else 
		timer <= timer +32'd1;
end

always@(posedge clk or negedge rst_n)
begin
    if(rst_n == 1'b0)
	begin
        light <= 4'b0000;
		adder <= 4'b0000;
	end
    else if (timer == 32'd0)
        light <= 4'b0001;
    else if (timer == 32'd12_499_999)
        light <= 4'b0010;
    else if (timer == 32'd24_999_999)
        light <= 4'b0100;
    else if (timer == 32'd36_499_999)
    begin
		light <= 4'b1000;
		if(adder_stop == 1'b1)
			adder <= adder;
		else if (adder_stop == 1'b0)
        	adder <= adder + 4'd1;
	end
	else if (timer == 32'd49_999_999)
		light <= adder;
end
		
endmodule