这是一个n比特计数器,可以向上向下计数,也可以设置计数值,采用异步低电平复位,并且使用generic语句设置参数。
1.新建工程:
2.编写程序,在ise里面有计数器模板:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jsq is
generic(jsq_width : integer := 8);
Port ( d_in : in STD_LOGIC_VECTOR (jsq_width-1 downto 0);
ce : in STD_LOGIC;
load : in STD_LOGIC;
updn : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q_out : out STD_LOGIC_VECTOR (jsq_width -1 downto 0));
end jsq;
architecture Behavioral of jsq is
signal count : STD_LOGIC_VECTOR (jsq_width-1 downto 0);
begin
process (clk,rst)
begin
if rst = '0' then
count <= (others => '0');
elsif clk='1' and clk'event then
if ce='1' then
if load = '1' then
count <= d_in;
else
if updn='1' then
count <= count+ 1;
else
count <= count - 1;
end if;
end if;
end if;
end if;
end process;
q_out <= count;
end Behavioral;
3.编写测试文件:
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jsq_tb IS
END jsq_tb;
ARCHITECTURE behavior OF jsq_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jsq
PORT(
d_in : IN std_logic_vector(7 downto 0);
ce : IN std_logic;
load : IN std_logic;
updn : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal d_in : std_logic_vector(7 downto 0) := X"0F";
signal ce : std_logic := '1';
signal load : std_logic := '0';
signal updn : std_logic := '1';
signal clk : std_logic := '0';
signal rst : std_logic := '1';
--Outputs
signal q_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: jsq PORT MAP (
d_in => d_in,
ce => ce,
load => load,
updn => updn,
clk => clk,
rst => rst,
q_out => q_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
ce <= '1','0' after 300ns , '1' after 400ns;
rst <= '0' after 15ns , '1' after 40ns;
updn <= '0' after 750ns;
load <= '1' after 500ns , '0' after 510ns;
END;