求助，用VHDL语言写的一个例化语句不对

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mimasuo is
port(CLK:in std_logic;
n:in std_logic_vector(9 downto 0);
set,check,close,back,ch:in std_logic;
led:out std_logic;
Digital0,Digital1,Digital2,Digital3:out std_logic_vector(6 downto 0));
end mimasuo;
architecture bhv of mimasuo1 is
component fenpin
port(clk_in:in std_logic;
clk_out:out std_logic);
end component;
component shuru
port(n:in std_logic_vector(9 downto 0);
sout:out std_logic_vector(3 downto 0));
end component;
component kongzhi
port( set,check,close,back,ch,clk:in std_logic;
dn:in std_logic_vector(3 downto 0);
sout:out std_logic_vector(15 downto 0);
led:out std_logic);
end component;
component shumaguan
port( x0,x1,x2,x3 : in std_logic_vector(3 downto 0);
digital0,digital1,digital2,digital3 : out std_logic_vector(6 downto 0));
end component;
signal net5 : std_logic_vector(3 downto 0);
signal net6 : std_logic;
signal net7 : std_logic_vector(3 downto 0);
signal net8 : std_logic_vector(3 downto 0);
signal net9 : std_logic_vector(3 downto 0);
signal net10 : std_logic_vector(3 downto 0);
begin
u1:fenpin port map(clk_in=>CLK,clk_out=>net6);
u2:shuru port map(n=>n,sout=>net5);
u3:kongzhi port map
(set,check,close,back,ch=>ch,net6,net5,led,
sout(3 downto 0)=>net7,sout(7 downto 4)=>net8,sout(11 downto 8)=>net9,sout(15 downto 12)=>net10);
u4:shumaguan port map(x0=>net7,x1=>net8,x2=>net9,x3=>net10,
digital0=>Digital0,digital1=>Digital1,digital2=>Digital2,digital3=>Digital3);
end bhv;