奇偶分频-verilog

//奇偶分频
module fre_div(
	input  clk,
	input  rst_n,
	output div_clk
    );
	 
	 reg div_clk1_odd;
	 reg div_clk2_odd;
	 reg div_clk3_even;
	 reg [2:0]cnt;
	 
	 always @ (posedge clk or negedge rst_n)
	 begin
		if(!rst_n)
			cnt <= 1'b0;
		else if (cnt==(div-1))
			cnt <= 1'b0;
		else
			cnt <= cnt+1'b1; 
	 end
	 
	 always @ (posedge clk or negedge rst_n)
	 begin
		if(!rst_n)
			div_clk1_odd <= 1'b0;
		else if (cnt == 3'd0)
			div_clk1_odd <= ~div_clk1_odd;
		else if (cnt == (div-1)/2)
			div_clk1_odd <= ~div_clk1_odd;
		else
			div_clk1_odd <=  div_clk1_odd;	
	 end
	 
	 always @(posedge clk or negedge rst_n)
	 begin
		if(!rst_n)
			div_clk2_odd <= 1'b0;
		else 
			div_clk2_odd <= div_clk1_odd;
	 end

	always @ (posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			div_clk3_even <= 1'b0;
		else if (cnt == 3'd0)
			div_clk3_even <= ~div_clk3_even;
		else if (cnt == div/2)
			div_clk3_even <= ~div_clk3_even;
		else
			div_clk3_even <=  div_clk3_even;	
	end

	assign div_clk = (div%2)==0 ? div_clk3_even : (div_clk1_odd)| (div_clk2_odd);
	
endmodule