过程部分1

//过程块
//1.  assign 语句中左侧赋值左侧是wire型，always赋值左侧是reg型，虽然都是组合逻辑。
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a&b;
    always@(*)begin
        out_alwaysblock = a&b;
    end
endmodule
//2.always中 在组合逻辑中，使用阻塞分配。在时序逻辑中，使用非阻塞分配。
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    assign out_assign = a^b;
    always@(*)begin
        out_always_comb = a^b;
    end
    always@(posedge clk)begin
        out_always_ff <= a^b;
    end
endmodule
//3.一个2选1的选择器 
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    assign out_assign = (sel_b1&sel_b2)? b:a;
    always@(*)begin
        if(sel_b1&sel_b2)
            out_always = b;
        else 
            out_always = a;
    end
endmodule
//4.if语句产生锁存器的问题       组合逻辑中，只有if的话，当出现其他不符合if的情况下，它的输出一般会保持不变，那么既然输出保持不变的话，出现其他情况时，会输出之前的结果，自然产生了一个锁存器，而这必然不符合组合逻辑的规则，解决这类问题的办法：对于if语句来说的话，只要加一个else语句，给输出一个默认值，从而解决
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
           shut_off_computer =0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else
           keep_driving = 0;
    end

endmodule

//5.case语句
module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            3'd0:out = data0;
            3'd1:out = data1;
            3'd2:out = data2;
            3'd3:out = data3;
            3'd4:out = data4;
            3'd5:out = data5;
            default:out = 3'd0;
        endcase
    end

endmodule
//6.4位的优先编码器  ：当给定输入位矢量时，输出矢量中第一个1位的位置
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    always@(*)begin
        casex (in)
            4'b1000:pos = 2'd3;
            4'bx100:pos = 2'd2;
            4'bxx10:pos = 2'd1;
            4'bxxx1:pos = 2'd0;
            default:pos = 0;
        endcase
    end
endmodule
//7.8位的优先编码器 
module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
    always@(*)begin
        casex (in)
            8'b1000_0000:pos = 3'd7;
            8'bx100_0000:pos = 3'd6;
            8'bxx10_0000:pos = 3'd5;
            8'bxxx1_0000:pos = 3'd4;
            8'bxxxx_1000:pos = 3'd3;
            8'bxxxx_x100:pos = 3'd2;
            8'bxxxx_xx10:pos = 3'd1;
            8'bxxxx_xxx1:pos = 3'd0;
            default:pos = 0;
        endcase
    end
endmodule
//8. 避免产生锁存器
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    always@(*)begin
        up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
        case(scancode)
            16'he06b: left = 1;
            16'he072: down = 1;
            16'he074: right =1;
            16'he075: up   = 1;
            default:{left,down,right,up} = 4'b0000;
        endcase
    end
endmodule