Lattice INPUT_SETUP PORT 计算方法

1. 下面这是我对reset引脚的约束，clk为36mhz

        INPUT_SETUP PORT "reset" 5.000000 ns CLKNET "clk" 

首先lattice 对于这个的定义是不准确的:（）

        "Input setup is the time difference between when the data arrives at its FPGA input pin, and when the next clock edge arrives as its FPGA pin."这是lattice时序分析的定义

        翻译过来：

        Input setup是数据到达其FPGA输入引脚和下一个时钟边缘到达其FPGA引脚 之间的时间差。

         它说的是到达fpga输入引脚，这种表示是不准确的的，应当是到达第一个FF触发器的D端，下一个时钟边缘到达FF触发器的CLK端。

以下是Dlamond关于这个约束的报告：

====================================================================== Preference: INPUT_SETUP PORT "reset" 5.000000 ns CLKNET "clk" ; Setup Analysis.             1 item scored, 0 timing errors detected.

--------------------------------------------------------------------------------

Passed:  The following path meets requirements by 1.283ns  

Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)  

 Source:         Port       Pad            reset    

Destination:    PDPW8KC    Port           addr_8__I_0_57(ASIC)  (to clk +)  

 Max Data Path Delay:     5.256ns  (26.8% logic, 73.2% route), 1 logic levels.  

 Min Clock Path Delay:    1.676ns  (0.0% logic, 100.0% route), 0 logic levels.  

Constraint Details:      

5.256ns delay reset to addr_8__I_0_57 less      

5.000ns offset reset to my_pll/PLLInst_0 (totaling 0.256ns) meets    

 1.676ns delay my_pll/PLLInst_0 to addr_8__I_0_57 less      

0.137ns LSRREC_SET requirement (totaling 1.539ns) by 1.283ns  

Physical Path Details:      

Data path reset to addr_8__I_0_57:    

Name    Fanout   Delay (ns)          Site               Resource

PADI_DEL    ---     1.410          5.PAD to        5.PADDI reset

ROUTE         4     3.846        5.PADDI to EBR_R8C21.RST  reset_c (to clk)                  

                             --------

                             5.256   (26.8% logic, 73.2% route), 1 logic levels.      

Clock path my_pll/PLLInst_0 to addr_8__I_0_57:    

Name    Fanout   Delay (ns)          Site               Resource

ROUTE        29     1.676     LPLL.CLKOP to EBR_R8C21.CLKR clk                  

                             --------                    

                              1.676   (0.0% logic, 100.0% route), 0 logic levels.

Report:    3.717ns is the minimum offset for this preference.

Weighted Slack: 1.283

=========================================================================

那么这个1.283是如何计算的

首先  dataDealy==5.256，Setup=0.137，时钟延迟为1.676，设置数据提前5ns到达

Weighted Slack=5+1.676-0.137-5.256=1.283