Verilog 中可综合和不可综合的结构——Synthesizable and Non-Synthesizable Verilog constructs

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已于 2024-01-14 09:13:43 修改

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分类专栏： FPGA 文章标签： Verilog fpga

于 2024-01-09 20:58:00 首次发布

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                    SynthesizableNon-Synthesizable
BasicIdentifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2’b11, 3’07, 32’d123, 8’hff), Signed constants (s) 3’bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists —— 标识符、转义标识符、大小常量 (b、o、d、h)、未大小常量 (2’b11、3’07、32’d123、8’hff)、有符号常量 (s) 3’bs101、module、endmodule、宏模块、ANSI 样式模块、任务和函数端口列表system tasks, real constants
Data typeswire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0] `;), N-dimensional arrays,real, time, event, tri0, tri1
Module instancesConnect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports, ——按名称、顺序连接端口、按顺序覆盖参数、按名称覆盖参数、连接到端口的常量、未连接的端口、连接到端口的表达式、Delay on built-in gates 内置门延迟
Generate statementsif,case,for generate, concurrent begin end blocks, genvar,
Primitivesand, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,User defined primitives 用户定义的原语 (UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos, rcmos, tranif0, tranif1, rtran, rtranif0, rtranif1,
Operators and expressions+, - (binary and unary)
Bitwise operations&, |, ^, ~^, ^~
Reduction operations&, |, ^, ~&, ~|, ~^, ^~, !, &&, || , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call=== , ! ==
Event controlevent or, @ (partial), event or using comma syntax, posedge, negedge (partial),Event trigger (->), delay and wait (#)
Bit and part selectsBit select, Bit select of array element, Constant part select, Variable part select ( +:, -`:), Variable bit-select on left side of an assignment ——位选择、数组元素的位选择、常量部分选择、变量部分选择（+:、-:）、赋值左侧的变量位选择
Continuous assignmentsnet and wire declaration, assignUsing delay
Procedural blocksalways (exactly one @ required),initial
Procedural statements;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),fork, join
Procedural assignmentsblocking (=), non-blocking (<=)force, release
Functions and tasksFunctions, tasks
Compiler directives`define, `undef,`resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include

                

	Synthesizable	Non-Synthesizable
Basic	Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2’b11, 3’07, 32’d123, 8’hff), Signed constants (s) 3’bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists —— 标识符、转义标识符、大小常量 (b、o、d、h)、未大小常量 (2’b11、3’07、32’d123、8’hff)、有符号常量 (s) 3’bs101、module、endmodule、宏模块、ANSI 样式模块、任务和函数端口列表	system tasks, real constants
Data types	wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0] `;), N-dimensional arrays,	real, time, event, tri0, tri1
Module instances	Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, Unconnected ports, Expressions connected to ports, ——按名称、顺序连接端口、按顺序覆盖参数、按名称覆盖参数、连接到端口的常量、未连接的端口、连接到端口的表达式、	Delay on built-in gates 内置门延迟
Generate statements	if,case,for generate, concurrent begin end blocks, genvar,
Primitives	and, or, nand, nor, xor, xnor,not, notif0, notif1, buf, bufif0, bufif1, tran,	User defined primitives 用户定义的原语 (UDPs), table, pullup, pulldown, pmos, nmos, cmos, rpmos, rnmos, rcmos, tranif0, tranif1, rtran, rtranif0, rtranif1,
Operators and expressions	+, - (binary and unary)
Bitwise operations	&, \|, ^, ~^, ^~
Reduction operations	&, \|, ^, ~&, ~\|, ~^, ^~, !, &&, \|\| , ==, !=, <, <=, >, >=, <<, >>, <<< >>>, {}, {n{}}, ?:, function call	=== , ! ==
Event control	event or, @ (partial), event or using comma syntax, posedge, negedge (partial),	Event trigger (->), delay and wait (#)
Bit and part selects	Bit select, Bit select of array element, Constant part select, Variable part select ( +:, -`:), Variable bit-select on left side of an assignment ——位选择、数组元素的位选择、常量部分选择、变量部分选择（+:、-:）、赋值左侧的变量位选择
Continuous assignments	net and wire declaration, assign	Using delay
Procedural blocks	always (exactly one @ required),	initial
Procedural statements	;, begin-end, if-else, repeat, case, casex, casez, default, for-while-forever-disable(partial),	fork, join
Procedural assignments	blocking (=), non-blocking (<=)	force, release
Functions and tasks	Functions, tasks
Compiler directives	`define, `undef,`resetall, `ifndef, `elsif, `line, `ifdef, `else, `endif, `include