Verilog 中可综合和不可综合的结构——Synthesizable and Non-Synthesizable Verilog constructs

疯狂的码泰君

已于 2024-01-14 09:13:43 修改

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分类专栏： FPGA 文章标签： Verilog fpga

于 2024-01-09 20:58:00 首次发布

本文链接：https://blog.csdn.net/qq_46264636/article/details/135489560

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本文概述了Verilog编程语言中的关键概念，包括可综合与不可综合标识符、转义标识符、不同类型的常量、模块结构、系统任务、数据类型、操作符、表达式、编译器指令等，以及程序流程控制和功能/任务的实现。

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   Synthesizable
   Non-Synthesizable
  
   Basic
   Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2’b11, 3’07, 32’d123, 8’hff), Signed constants (s) 3’bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists —— 标识符、转义标识符、大小常量 (b、o、d、h)、未大小常量 (2’b11、3’07、32’d123、8’hff)、有符号常量 (s) 3’bs101、module、endmodule、宏模块、ANSI 样式模块、任务和函数端口列表
   system tasks, real constants
  
   Data types
   wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0] `;), N-dimensional arrays,
   real, time, event, tri0, tri1
  
   Module instances
   Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, U

	Synthesizable	Non-Synthesizable
Basic	Identifiers, escaped identifiers, Sized constants (b, o, d, h), Unsized constants (2’b11, 3’07, 32’d123, 8’hff), Signed constants (s) 3’bs101, module, endmodule, macromodule, ANSI-style module, task, and function port lists —— 标识符、转义标识符、大小常量 (b、o、d、h)、未大小常量 (2’b11、3’07、32’d123、8’hff)、有符号常量 (s) 3’bs101、module、endmodule、宏模块、ANSI 样式模块、任务和函数端口列表	system tasks, real constants
Data types	wire, wand, wor, tri, triand, trior, supply0, supply1, trireg (treated as wire), reg, integer, parameter, input, output, inout, memory(reg [7:0] x [3:0] `;), N-dimensional arrays,	real, time, event, tri0, tri1
Module instances	Connect port by name, order, Override parameter by order, Override parameter by name, Constants connected to ports, U