FPGA学习检测输入信号上升沿及下降沿练习

上升沿及下降沿检测练习

设计目标：输入一个方波信号（50%占空比），输出其频率（要求判定其上升沿下降沿来判定频率）

时序图

代码

exsig_edge

 module exsig_edge (
    input wire clk,
    input wire signal,
    input wire rst_n,
    output reg [31:0]F
);
    
reg sig_r1;
reg sig_r2;
reg posedge_flag;
reg negedge_flag;
reg [31:0]cnt;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        sig_r1 <= 1'b0;
    end
    else if (signal == 1'b1) begin
        sig_r1 <= 1'b1;
    end
    else  begin
        sig_r1 <= 1'b0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        sig_r2 <= 1'b0;
    end
    else if (sig_r1) begin
        sig_r2 <= 1'b1;
    end
    else  begin
        sig_r2 <= 1'b0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        posedge_flag <= 1'b0;
    end
    else if (sig_r1 & ~sig_r2) begin
        posedge_flag <= 1'b1;
    end
    else  begin
        posedge_flag <= 1'b0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        negedge_flag <= 1'b0;
    end
    else if (~sig_r1 & sig_r2) begin
        negedge_flag <= 1'b1;
    end
    else  begin
        negedge_flag <= 1'b0;
    end
end



always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        cnt <= 32'd0;
    end
    else if (posedge_flag == 1'b1) begin
        cnt <= 32'd0;
    end
    else if (negedge_flag == 1'b0) begin
        cnt <= cnt;
    end
    else  begin
        cnt <= cnt + 32'd1;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        F <= 32'd0;
    end
    else if (negedge_flag == 1'b1) begin
        F <= 50000000 / (2*(cnt + 32'd1)); 
    end
    else  begin
        F <= F;
    end
end



endmodule

tb文件

`timescale 1ns/1ps

module exsig_edge_tb ();
    
reg clk;
reg rst_n;
reg signal;
wire [31:0]F;

initial begin
    clk = 1'b0;
    rst_n = 1'b0;
    signal = 1'b0;
    #2
    rst_n = 1'b1;
end

always #10 clk = ~clk;
always #20.1 signal = ~signal;

exsig_edge exsig_edge_1(
    .clk(clk),
    .signal(signal),
    .rst_n(rst_n),
    .F(F)
);

endmodule

仿真结果