FPGA（7）DAC（DDS)

module  dds_ctrl(sys_clk,sys_rst,wave_sel,A_word,F_word,P_word,data_out);

    input   wire    sys_clk,sys_rst;
    input   wire    [3:0]   wave_sel;
    input   wire    [10:0]  F_word;
    input   wire    [11:0]  P_word;
    input   wire    [7:0]   A_word;
    output  wire    [7:0]   data_out;
reg     [11:0]  freq_regcnt;

reg     [11:0]  rom_addr_reg;
wire     [7:0]   datain_out;


parameter   sin_wave=4'b0001;  //正弦波
parameter   fang_wave=4'b0010;
parameter   juci_wave=4'b0100;
parameter   sanjiao_wave=4'b1000;
//相位累加器
always@(posedge sys_clk or negedge  sys_rst)
begin
    if(!sys_rst)
        freq_regcnt<=12'd0;
    else
        freq_regcnt<=freq_regcnt+F_word;
end


//产生rom地址(depth=2^12,bit=8)
always@(posedge sys_clk or negedge  sys_rst)
begin
    if(!sys_rst)
        begin
            rom_addr_reg<=12'd0;
        end
    else
            rom_addr_reg<=P_word+freq_regcnt;
end





sin_8x12    sin_8x12_inst (
.address ( rom_addr_reg ),
.clock ( sys_clk ),
.q ( datain_out )
);


assign  data_out=datain_out-A_word;


endmodule











    

module  DDS(sys_clk,sys_rst,data_out,clk_out);

    input   wire    sys_clk,sys_rst;
    output  wire    [7:0]   data_out;
    output  wire    clk_out;


assign  clk_out=~sys_clk;
    
    
dds_ctrl(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wave_sel(1'b1),
.A_word(8'd0),
.F_word(11'd1024),
.P_word(12'd2048),
.data_out(data_out)
);

endmodule