3.2.5.15 Serial receiver and datapath

现在您有了一个有限状态机，可以识别何时在串行比特流中正确接收到字节，添加一个数据路径来输出正确接收到的数据字节。out_byte需要在done为1时有效，否则不在乎。

请注意，串行协议首先发送最低有效位。

无错误：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Use FSM from Fsm_serial
	parameter R=4'd0,S0=4'd1,S1=4'd2,S2=4'd3,S3=4'd4,S4=4'd5,S5=4'd6,S6=4'd7,S7=4'd8,S8=4'd9,S9=4'd10,E=4'd11;
    reg [3:0]state,next_state,temp_state;
    reg [3:0]num;
    reg [7:0]out_byte_temp;
    always @(posedge clk) begin
        if(reset)
            state<=R;
        else
            state<=next_state;
    end
    always @(*) begin
        case (state)
            R:begin
                if(in)
                    next_state<=R;
                else
                    next_state<=S0;
            end
            S0:next_state<=S1;
            S1:next_state<=S2;
            S2:next_state<=S3;
            S3:next_state<=S4;
            S4:next_state<=S5;
            S5:next_state<=S6;
            S6:next_state<=S7;
            S7:next_state<=S8;
            S8:begin
                if(in)
                    next_state<=S9;
                else 
                    next_state<=E;
            end
            E:begin
                if(in)
                    next_state<=S9;
                else
                    next_state<=E;
            end
            S9:begin
                if(in)
                    next_state<=R;
                else
                    next_state<=S0;
            end
            
        endcase
    end
    always@(posedge clk)begin
        temp_state<=state;
    end
    always@(*)begin
        if((temp_state==E)&(state==S9))
            done=0;
        else if(state==S9)
            done=1;
        else
            done=0;
    end
    // New: Datapath to latch input bits.
    always@(posedge clk)begin
        if(reset)begin
            num<=0;
            out_byte_temp<=8'd0;
        end
        else if((num<4'd7)&((state==S0)|(state==S1)|(state==S2)|(state==S3)|(state==S4)|(state==S5)|(state==S6)))begin
            num<=num+1;
            out_byte_temp[num]<=in;
        end
        else if((num==4'd7)&(state==S7))begin
            num<=0;
            out_byte_temp[num]<=in;
        end
        else if((done==1)|(state==E)|(state==R))begin
            num<=0;
            out_byte_temp[num]<=out_byte_temp[num];
        end
        else begin
            num<=num;
            out_byte_temp[num]<=out_byte_temp[num];
        end
    end
    assign out_byte=out_byte_temp;
endmodule

同样在设计输出上花费了很长时间，而且设计的输出很复杂

实际上可以不用计数器，而在状态转移中直接将in输入给out_type

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Use FSM from Fsm_serial
	parameter R=4'd0,S0=4'd1,S1=4'd2,S2=4'd3,S3=4'd4,S4=4'd5,S5=4'd6,S6=4'd7,S7=4'd8,S8=4'd9,S9=4'd10,E=4'd11;
    reg [3:0]state,next_state,temp_state;
    reg [3:0]num;
    reg [7:0]out_byte_temp;
    always @(posedge clk) begin
        if(reset)
            state<=R;
        else
            state<=next_state;
    end
    always @(*) begin
        case (state)
            R:begin
                if(in)
                    next_state<=R;
                else
                    next_state<=S0;
            end
            S0: begin next_state<=S1;out_byte_temp[0]<=in; end
            S1:begin next_state<=S2;out_byte_temp[1]<=in; end
            S2:begin next_state<=S3;out_byte_temp[2]<=in; end
            S3:begin next_state<=S4;out_byte_temp[3]<=in; end
            S4:begin next_state<=S5;out_byte_temp[4]<=in; end
            S5:begin next_state<=S6;out_byte_temp[5]<=in; end
            S6:begin next_state<=S7;out_byte_temp[6]<=in; end
            S7:begin next_state<=S8;out_byte_temp[7]<=in; end
            S8:begin
                if(in)
                    next_state<=S9;
                else 
                    next_state<=E;
            end
            E:begin
                if(in)
                    next_state<=S9;
                else
                    next_state<=E;
            end
            S9:begin
                if(in)
                    next_state<=R;
                else
                    next_state<=S0;
            end
            
        endcase
    end
    always@(posedge clk)begin
        temp_state<=state;
    end
    always@(*)begin
        if((temp_state==E)&(state==S9))
            done=0;
        else if(state==S9)
            done=1;
        else
            done=0;
    end
    // New: Datapath to latch input bits.
    
    assign out_byte=done?out_byte_temp:8'd0;
endmodule