vivado报错 遇到困难不要怕

2023.8.21

[Designutils 20-1733] GTHE2 is not supported for the device xc7k420tffg1156-2

事情经过：在给工程换板子时候，ip_update日志显示-Upgrade has removed port 'gt0_qpll_lock_in'；

gt0_qpll_lock_in这个信号总是被优化掉了。

后续是把srio的IP核解锁跟新。

2023.8.21

[DRC REQP-1960] GTXE2_valid_QPLL_input_clock_driver: GTXE2_CHANNEL cell u_sata_platform/gtwizard_support_i/gtwizard_init_i/inst/gtwizard_i/gt0_gtwizard_i/gtxe2_i: The u_sata_platform/gtwizard_support_i/gtwizard_init_i/inst/gtwizard_i/gt0_gtwizard_i/gtxe2_i/QPLLCLK input clock pin may only be driven by a GTXE2_COMMON or another GTXE2_CHANNEL, instead of u_sata_platform/gtwizard_support_i/common0_i/gthe2_common_i

后续。。。换成srio例程的common模块就不报错了

2023.8.23

[Xicom 50-38] xicom: Unable to connect to debug core(s) on the target device. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

事情经过：还是因为换了板子，软件有一个复位的操作，复位后一直报找不到ila了；

后续。。。这个问题整整折磨了三天多，从修改程序到重新建程序，最后使用原本程序才发现是设备重启后会自动烧录固有bit，ila都不匹配怎么能看ila呢。研究了那么久的代码竟不如破罐子破摔。

2023.8.28

ERROR: [Labtools 27-3165] End of startup status: LOW

线没接好。

2023.9.25

[DRC REQP-43] must_use_ref_clock: GTHE2_CHANNEL cell siro0_share_111_inst/chnl_loop[0].design_1_wrapper_isnt/design_1_i/srio_gen2_0/inst/srio_gt_wrapper_inst/inst/g