HDLBits_Fsm hdlc

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    reg [2:0] count;
    reg [2:0] state,next_state;
    parameter [2:0] IDLE = 3'b000,
    				RECEIVE = 3'b001,
    				DISCARD = 3'b011,
    				FLAG = 3'b101,
    				ERROR = 3'b111;

    always @(*) begin
        case(state) 
            IDLE:begin
                next_state = in?RECEIVE:IDLE;
            end
            
            RECEIVE:begin
                case(count)
                    3'd4:next_state = in?RECEIVE:DISCARD;
                    3'd5:next_state = in?ERROR:FLAG;
                    default:next_state = in?RECEIVE:IDLE;
                endcase
            end
            
            DISCARD:begin
                next_state = in?RECEIVE:IDLE;
            end
            
            FLAG:begin
                next_state = in?RECEIVE:IDLE;
            end
            
            ERROR:begin
                next_state = in?ERROR:IDLE;
            end
            
            default:next_state = IDLE;
        endcase 
    end

    always @(posedge clk) begin
        if(reset) begin
           	count<=0;
			state<=IDLE;
        end
        else begin
            case(state)
                RECEIVE:count<=count+1'b1;
                default:count<=0;
            endcase
            state <= next_state;
        end
    end
    
    assign disc = (state==DISCARD);
    assign flag = (state==FLAG);
    assign err  = (state==ERROR) ;
endmodule

这道题应该in=0代表标志位回到IDLE的状态判断。

初始时，笔者以为in=0是IDLE跳转到DATA Receive的标志位，故功能一直不正确。该处应该是接收第一个1到来并计数就可以。