HDLBits / fsm / hdlc

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,flag0=7,disc0=8,err0=9;
    reg [3:0] state ,next_state;
    
   //状态转移条件
    always@(*)begin
        case(state)
            s0: next_state = in ? s1:s0;
            s1: next_state = in ? s2:s0;
            s2: next_state = in ? s3:s0;
            s3: next_state = in ? s4:s0;
            s4: next_state = in ? s5:s0;
            s5: next_state = in ? s6:disc0;
            s6: next_state = in ? err0:flag0;
            flag0: next_state = in ? s1:s0;
            disc0: next_state = in ? s1:s0;
            err0: next_state = in ?  err0:s0;  
            default:next_state = s0;
        endcase
    end
    //状态转移过程
    always@(posedge clk)begin
        if(reset)
            state <= s0;
        else
            state <= next_state;
    end
    
    //output
    assign disc = (state == disc0);
    assign err = (state == err0);
    assign flag = (state == flag0);
endmodule

要注意err0的的下一个状态转移。