问题:QUARTUS报错:Current license file does not support the EP4CGX15BN11C7 device
解决方法:将我自己电脑中的sys_cpt.dll发给用户的电脑中即可解决问题,百度网盘中加了sys_cpt.dll文件,届时可以直接发送给用户替换点bin64和bin中的sys_cpt.dll文件即可!
2023.3.30
同样的问题,软件版本为18.0,重新破解了一下解决了问题(crack拷贝到bin64........)
cannot match operand(s)in the condition to the corresponding edges in the enclosing event control
Error (10170): Verilog HDL syntax error at shumaguan.v(82) near text Â
Error (10170): Verilog HDL syntax error at shumaguan.v(82) near text "Â"; expecting an operand
Error (10170): Verilog HDL syntax error at shumaguan.v(83) near text Â
Error (10170): Verilog HDL syntax error at shumaguan.v(83) near text "Â"; expecting
解决方法:
删除红色圈内的空格!
Error (125091): Tcl error: ERROR: Illegal assignment: IP_GENERATED_DEVICE_FAMILY. Specify a legal as
解决方法:
Error (176310): Can't place multiple pins assigned to pin location Pin_13 (IOPAD_X0_Y17_N21)
Info (176311): Pin I_sw_counter is assigned to pin location Pin_13 (IOPAD_X0_Y17_N21)
Info (176311): Pin ~ALTERA_DATA0~ is assigned to pin location Pin_13 (IOPAD_X0_Y17_N21)
解决方案:
这些引脚是双功能引脚,配置后才能使用(Assignments->Device-> Device and Pin Options->Dual-Purpose Pins->"Value"->"Use as regular I/O")
问题:Error (12006): Node instance "u_lcd_display_image" instantiates undefined entity "lcd_display_image". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
原因及解决方法:顶层文件例化ip核的时候必须使用创建ip核时候的名字!!!
问题:Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly.
解决方法:我用的是modelsim 10.7版本的,根据其他网友的方法吧simulation setting下面的两个novopt指令删除之后,仿真依然报错,并且我的modelsim.ini文件里面的voptflow就是1. 最后我重新下载了一个modlesim-alterea,根据quaruts仿真提示,modelsim-altera的优先级回避modelsim更高。之后再跑仿真问题就解决了
问题:Top-level entity “nco“ is ambiguous
原因及解决方法:这个错误原因是nios中的名字跟顶层文件的名字重复了(或者说有与顶层名字重复的例化文件啥的),改了即可。引用自http://t.csdnimg.cn/W0NRY