LPDDR5协议解析 ZQ

简单来说:ZQ是一个连接在VDDQ和DRAM ZQ pin上的一个精确电阻，阻值为240Ω。ZQ一般是在PCB板上，因此基本上不随着外界温度和电压的变化而变化。但DRAM内部用到的各种电阻，比如ODT等是会随着温度和电压而漂移的，ZQ training/calibration 就是为了解决这种漂移，即通过一个精准的，不跟随外界环境变化的已知阻值的电阻，来校准内部的会随VT变化的电阻，使得内部的电阻能回到漂移之前的阻值范围。

LPDDR5中的ZQ calibration

4.2.1 ZQ Calibration
Two ZQ calibration modes are supported—Background Calibration or Command-Based Calibration. In Background Calibration mode, calibration of the output driver and CA/DQ ODT impedance across process, temperature, and voltage occurs in the background of device operation and is designed to eliminate any need for coordination among channels (that is, it allows for channel independence) within a single package. Systems may also select Command-Based Calibration mode, which operates in a fashion similar to LPDDR4 devices. Command-Based Calibration mode is selected by setting MR28 OP[5]=1B. ZQ re-calibration may be required as the LPDDR5 SDRAM voltage and/or temperature changes due to changes in the system environment. ZQ calibration can only be performed when the VDDQ voltage is set
to nominal 0.5v DC or above (i.e., when DVFSQ is not active). In Background Calibration mode, the calibration shall be halted by the memory controller setting ZQ Stop when VDDQ is set to a nominal DC level below 0.5v or when VDDQ is being slewed between levels (i.e., when DVFSQ is active). In Command-Based mode, ZQCal Start commands are illegal when DVFSQ is active unless ZQ Stop is set.
See 4.2.1.2 for more information.
Changing CA ODT values (MR11-OP[6:4]) and/or DQ ODT values (MR11-OP[2:0]) will not alter the existing recalibration scheme, therefore there is no need for immediate recalibration.

解读：在LPDDR5中，用户可以选择两张ZQC的方式，一种是background ZQ，一种是command-based ZQ。

background ZQ

即DRAM自己进行周期性的ZQC，得到合适的driver/ODT的电阻值，而不用显式的发送cal命令，而用户只需要在合适的时间发送ZQ latch命令，帮助DRAM将周期性的ZQC得到合适的电阻值更新到driver/ODT上就可以。为什么不能更加自主化，自己ZQC出的值自己ZQL？因为ZQL涉及到阻值的变化（因为锁存后，更新的阻值正式生效），如果正在进行读写，突然改变阻值会使得读写数据不准确，而颗粒本身是不知道什么时候会发读写，也没法将正在路上的读写暂停，所以只能在用户没有读写的时候发送ZQ latch命令更新阻值。

command-based ZQ

需要显式的发送ZQC命令，如果不发送命令DRAM不会做电阻的校准，用户可以自由的选择在需要的时候进行ZQC命令的发送，在等待一定时间后保证ZQC的结束，再发送ZQL来发送更新电阻值。

由于ZQ电阻（精确240Ω）是接在VDDQ和ZQ pin之间的，因此当进行ZQC的时候对VDDQ有要求，VDDQ必须≥0.5V，当因为功耗的需求需要进行DVFSQ时，ZQ需要被暂停。暂停ZQ是通过一个MRW来完成的，即MR28 OP[1]。无论是background ZQ还是command-based ZQ， 在VDDQ<0.5V的时候都要通过MRW来stop ZQ。

4.2.1.1 Calibration During Powerup and Initialization
ZQ calibration is automatically performed by all LPDDR5 die during the initialization/powerup sequence
before Td, as shown in Figure 13. A ZQCal Latch command shall be issued to all LPDDR5 die on or after
Tg regardless of the state of ZQUF. ZQ Calibration mode selection may be changed any time after Tf.

解读：P28图中，Tg时刻有一个latch命令，那说明之前颗粒已经做过ZQC了，该ZQC是在解复位之后自动做的，在Td时刻（t