MSP432学习笔记8:定时器A_PWM驱动舵机

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开发板型号:MSP432P401r

今日得以继续我的MSP432电赛速通之路,文首提供本次学习实践项目文件。

注:我笔记实践都是从原始空项目工程文件开始配置的。

有道是        —_—_—_—_—

“山无重数周遭碧,花不知名分外娇”    “曲中人不见,江上数峰青” .........

连绵不绝的山峦,起伏有序,高峰紧薄低谷,诗意酝在其中。

  像极了我们今日要学习的——定时器PWM输出

目录

空项目传送门:

上篇文章 定时器A中断  传送门:

本篇文章实践项目传送门:

基础知识:

MSP432定时器A对应引脚图:

定时器输出PWM相关库函数:

定时器输出PWM一般步骤:

1.配置GPIO复用:

2.配置结构体:

对于PWM的频率占空比的计算,我们可以通过以下公式进行计算:

3.初始化定时器:

尝试驱动舵机:

以下是我的9g舵机,以及驱动原理:

以下为舵机控制有关的源码:

以下为成功下载测试视频:


空项目传送门:

https://download.csdn.net/download/qq_64257614/87781382?spm=1001.2014.3001.5503

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MSP432 低功耗高性能并存10.1 Digital I/O Introduction The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable interrupts for ports (available for certain ports only) • Independent input and output data registers • Individually configurable pullup or pulldown resistors • Wake-up capability from ultra-low power modes (available for certain ports only) • Individually configurable high drive I/Os (available for certain I/Os only) Devices within the family may have up to eleven digital I/O ports implemented (P1 to P10 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors. Certain ports have interrupt and wake-up capability from ultra-low power modes (see device specific data sheet for ports with interrupt and wake-up capability). Each interrupt can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All interrupts are fed into an encoded Interrupt Vector register, allowing the application to determine which sub-pin of a port has generated the event. Individual ports can be accessed as byte-wide ports or can be combined into half-word-wide ports. Port pairs P1 and P2, P3 and P4, P5 and P6, P7 and P8, and so on, are associated with the names PA, PB, PC, PD, and so on, respectively. All port registers are handled in this manner with this naming convention. The main exception are the interrupt vector registers, for example, interrupts for ports P1 and P2 must be handled through P1IV and P2IV, PAIV does not exist. When writing to port PA with half-word operations, all 16 bits are written to the port. When writing to the lower byte of port PA using byte operations,

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