时钟分频电路设计,可以分为偶数分频和奇数分频;
偶数分频实例:
二分频:
// 二分频电路
module clk_div2(clk_out, reset, clk_in);
input reset;
input clk_in;
output clk_out;
reg clk_out;
always @(posedge clk_in) begin
if(!reset)
clk_out <= 0;
else
clk_out <= ~clk_out;
end
endmodule
四分频:
module clk_div4(clk_out, reset, clk_in);
input clk_in;
input reset;
output clk_out;
reg clk_out;
reg [3:0] cnt;
always @(posedge clk_in) begin
if(!reset) begin
cnt <= 0;
clk_out <= 0;
end
/* if(cnt == 1) begin */
else if(cnt == 1) begin
clk_out <= ~clk_out;
cnt <&