选题五 篮球24秒计时

一、实验步骤
1、打开Modelsim,新建项目

2、创建项目名称


3、新建文件，建立所需要的文件，在Add file as type中选择Verilog

4、将代码全部输入到文件中，并保存

5、然后点击编译，验证代码是否正确，全部正确后就可以进行仿真


6、添加波形图并放大

二、实验代码
源代码
module digital(TimerH,TimerL,over,Reset,Stop,clk);
output [6:0]TimerH;
output [6:0]TimerL;
output over;
input Reset;
input Stop;
input clk;
wire [1:0]H;
wire [3:0]L;
wire clk_1;
fenpin UO (.clk(clk),.clk_old(clk_1));
basketballtimer U1(over, H[1:0],L[3:0], Reset, Stop,clk_1);
CD4511 U2 (TimerH[6:0], {2’b00,H[1:0]});
CD4511 U3 (TimerL[6:0], L[3:0]);
endmodule

module fenpin (clk_old, clk);
output clk_old;
input clk;
reg[24:0] count;
reg clk_old;
always @(posedge clk)
begin
if(count==25’b1_1001_0000_0000_0000_0000_0000)
begin
clk_old<=~clk_old;
count<=0;
end
else
count<=count+1;
end

endmodule

module basketballtimer (Over,TimerH, TimerL,Reset,Stop,clk_1);
output Over;
output [1:0]TimerH;
output [3:0]TimerL;
input Reset;
input Stop;
input clk_1;

reg [4:0] Q;

assign Over =(Q== 5 'd0);
assign TimerH=Q/10;
assign TimerL=Q%10;

always @(posedge clk_1 or negedge Reset or negedge Stop)
begin
if(~Reset)
Q <= 5’d23;
else
begin
if(~Stop)
Q <= Q;
else
begin
if(Q>5’d0)
Q <= Q - 1’b1;
else
Q <=Q;
end
end
end
endmodule

module CD4511 (Y,A);
output reg [6:0]Y;
input [3:0]A;
always @(*)
begin
case(A)
4’d0: Y<=7’b1000_000;
4 'd1: Y<=7’b1111_001;
4 'd2: Y<=7’b0100_100;
4’d3: Y<=7’b0110_000;
4 'd4:Y<=7’b0011_001;
4 'd5: Y<=7’b0010_010;
4 'd6: Y<=7’b0000_010;
4 'd7: Y<=7’b1111_000;
4 'd8: Y<=7 'b0000_000;
4’d9: Y<=7’b0010_000;
default: Y<=7’b1000_000;
endcase
end
endmodule
测试代码
module tbdigital;
wire [6:0]TimerH;
wire [6:0]TimerL;
wire over;
reg Reset;
reg Stop;
reg clk;
initial
begin
clk=0;
Reset=1;
Stop=1;
#10 Reset=0;
#20 Reset=1;
#200 Stop=0;
#50 Stop=1;
@ (posedge over);
#10 $stop;
end

always #5 clk=~clk;
digital idigital (TimerH, TimerL, over,Reset, Stop, clk);
endmodule

三、实验过程视频链接
https://v.qq.com/x/page/u3255a1gqeb.html