xilinx UART-lite AXI4接口testbench

升级到vivado2015后，为了升级以及zynq系列FPGA MPSOC考虑，xilinx后续IP将都支持AXI接口，但UART的设计并没有找到example/wavform/testbench，搞了大半天才把串口调通。

串口波特率设置为115200，则发送一个bit的时间是：

; 10000/1152
	~8.68055555555555555556us
; 

再来看仿真图的结果（两个时间戳标示的是一个比特的时间宽度，120.515-111.875=8.640us）：和理论计算的值非常接近。

接下来，给出uart-lite的配置页面图

接下来是简单的testbench：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: shichao
// 
// Create Date: 04/14/2016 03:15:22 PM
// Design Name: 
// Module Name: TB_uart
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module TB_uart;
    reg s_axi_aclk;
    reg s_axi_aresetn;
    wire interrupt;
    reg [3 : 0] s_axi_awaddr;
    reg s_axi_awvalid;
    wire s_axi_awready;
    reg [31 : 0] s_axi_wdata;
    reg [3 : 0] s_axi_wstrb;
    reg s_axi_wvalid;
    wire s_axi_wready;
    wire [1 : 0] s_axi_bresp;
    wire s_axi_bvalid;
    reg s_axi_bready;
    reg [3 : 0] s_axi_araddr;
    reg s_axi_arvalid;
    wire s_axi_arready;
    wire [31 : 0] s_axi_rdata;
    wire [1 : 0] s_axi_rresp;
    wire s_axi_rvalid;
    reg s_axi_rready;
    reg  rx;
    wire tx;
    

    
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axi_uartlite_0 unt (
  .s_axi_aclk(s_axi_aclk),        // input wire s_axi_aclk
  .s_axi_aresetn(s_axi_aresetn),  // input wire s_axi_aresetn
  .interrupt(interrupt),          // output wire interrupt
  .s_axi_awaddr(s_axi_awaddr),    // input wire [3 : 0] s_axi_awaddr
  .s_axi_awvalid(s_axi_awvalid),  // input wire s_axi_awvalid
  .s_axi_awready(s_axi_awready),  // output wire s_axi_awready
  .s_axi_wdata(s_axi_wdata),      // input wire [31 : 0] s_axi_wdata
  .s_axi_wstrb(s_axi_wstrb),      // input wire [3 : 0] s_axi_wstrb
  .s_axi_wvalid(s_axi_wvalid),    // input wire s_axi_wvalid
  .s_axi_wready(s_axi_wready),    // output wire s_axi_wready
  .s_axi_bresp(s_axi_bresp),      // output wire [1 : 0] s_axi_bresp
  .s_axi_bvalid(s_axi_bvalid),    // output wire s_axi_bvalid
  .s_axi_bready(s_axi_bready),    // input wire s_axi_bready
  .s_axi_araddr(s_axi_araddr),    // input wire [3 : 0] s_axi_araddr
  .s_axi_arvalid(s_axi_arvalid),  // input wire s_axi_arvalid
  .s_axi_arready(s_axi_arready),  // output wire s_axi_arready
  .s_axi_rdata(s_axi_rdata),      // output wire [31 : 0] s_axi_rdata
  .s_axi_rresp(s_axi_rresp),      // output wire [1 : 0] s_axi_rresp
  .s_axi_rvalid(s_axi_rvalid),    // output wire s_axi_rvalid
  .s_axi_rready(s_axi_rready),    // input wire s_axi_rready
  .rx(rx),                        // input wire rx
  .tx(tx)                        // output wire tx
);

    parameter Clockperiod = 10;
    
    reg[7:0] channel;
    reg[31:0] config_data;
    initial begin
        // generate clk
        s_axi_aclk =0;
        forever s_axi_aclk =  #(Clockperiod/2) ~s_axi_aclk;
        //always #(Clockperiod/2) s_axi_aclk = ~s_axi_aclk;
    end
    
    initial begin
        s_axi_aresetn = 0;
        s_axi_arvalid = 0;
        s_axi_wvalid = 0;
        channel = 6;
        config_data = 32'h00000003;

     #50
        s_axi_aresetn = 1;
        s_axi_bready =1;
        s_axi_araddr = 1;
        s_axi_araddr = 0;
       // s_axi_arvalid = 1;
      s_axi_wvalid = 1;
      

    #10    
    s_axi_awaddr = 4'h0c;
    s_axi_awvalid =1'b1;
    s_axi_wdata = 32'h00000003; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero
    //s_axi_rdata = 32'h00000055;
    s_axi_wstrb = 4'b00;  
    #10;
    s_axi_awaddr = 4'h0c;
    s_axi_awvalid =1'b1;
    s_axi_wdata = 32'h00000000; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero
   // s_axi_rdata = 32'h000000aa;
    s_axi_wstrb = 4'b01;   
      
    #10;
    s_axi_awaddr = 4'h04;
    s_axi_wdata = 32'h0000000f5; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero
   // s_axi_awvalid =1'b1;
    s_axi_wstrb = 4'b00;  
     
    #10;
    s_axi_awaddr = 4'h04;
    s_axi_wdata = 32'h00000080; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero
 
   // s_axi_awvalid =1'b1;
    s_axi_wstrb = 4'b10;  
    
    #50;
    s_axi_awaddr = 4'h04;
    s_axi_wdata = 32'h000000aa; // I have a real input signal, so the upper half (corresponding to the immaginary part) is zero
 
   // s_axi_awvalid =1'b1;
    s_axi_wstrb = 4'b10;  
    
    #10
    s_axi_wvalid = 0;
    
    end

endmodule