Verilog刷题笔记45

题目：Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.
Build this circuit.

解题：

module top_module (
    input clk,
    input x,
    output z
); 
    wire [2:0]size;
    dtouch state0(
        .Clk(clk),
        .d(x^size[0]),
        .q(size[0])
    );
    dtouch state1(
        .Clk(clk),
        .d(x&(~size[1])),
        .q(size[1])
    );
    dtouch state2(
    	    .Clk(clk),
        	.d(x|(~size[2])),
            .q(size[2])
    );
    assign z=~(size[0]|size[1]|size[2]);
        

endmodule
       
        module dtouch(
        	input Clk,
            input d,
            output q
        
        );
            always@(posedge Clk)begin
                q<=d;
            end
        endmodule

结果正确：

注意点：该题有三个门电路，三个触发器，考虑用例化的办法实现。