STM32F4独立看门狗IWDG

Figure 213. Independent watchdog block diagram 

The devices have two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. 

Both watchdog peripherals (Independentand Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value.

The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. 

The window watchdog (WWDG) clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior.

The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy
constraints. 

The WWDG is best suited to applications which require the watchdog to react within an accurate timing window.