双端口RAM具有两套地址总线,一套用于读数据,另一套用于写数据,两者可以分别进行操作。
module ram_dual(clk1,clk2,q,addr_in,addr_out,d,we,rd);
input clk1,clk2,we,rd;
input [2:0] addr_in,addr_out;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
reg [7:0] mem [7:0];
always @ (posedge clk1) begin
if(we)
mem[addr_in] <= d;
end
always @ (posedge clk2) begin
if(rd)
q <= mem[addr_out];
end
endmodule
`timescale 1ns/1ns
module ram_dual_tb;
reg clk1,clk2,we,rd;
reg [2:0] addr_in,addr_out;
reg [7:0] d;
wire [7:0] q;
ram_dual n1 (clk1,clk2,q,addr_in,addr_out,d,we,rd);
initial begin
clk1 = 0; clk2 = 0; we = 1; rd = 0; addr_in = 0; addr_out = 0; d = 0;
#320 we = 0;
rd = 1;
end
always begin
#10 clk1 = ~clk1;
clk2 = ~clk2;
end
initial begin
repeat(7) begin
#40 addr_in = addr_in+1;
d = d+2;
end
#40 repeat (7)
#40 addr_out = addr_out+1;
end
//#200 $finish;
endmodule