【sv】assert-1

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已于 2024-08-28 19:54:08 修改

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于 2022-01-25 02:10:07 首次发布

本文链接：https://blog.csdn.net/stm32stu/article/details/122678197

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assert相关，过程记录

1.fsdb dump sva的结果，可以在fsdb中查看assert的具体信息，如下图在这里插入图片描述

vcs仿真单个文件，进行波形dump

> vcs -full64 -sverilog xxx.sv -R -debug_pp -LDFLAGS "-Wl,--rpath,/$NOVAS_HOME/share/PLI/VCS/LINUX64" -P $NOVAS_HOME/share/PLI/VCS/LINUX64/novas.tab $NOVAS_HOME/share/PLI/VCS/LINUX64/pli.a -lca -kdb -top test

使用ucli的方式进行波形dump

> vcs -full64 -sverilog xxx.sv -R -debug_pp -LDFLAGS "-Wl,--rpath,/$NOVAS_HOME/share/PLI/VCS/LINUX64" -P $NOVAS_HOME/share/PLI/VCS/LINUX64/novas.tab $NOVAS_HOME/share/PLI/VCS/LINUX64/pli.a -lca -kdb -top test -ucli -i ucli.tcl

在环境中设置fsdb dump
在这里插入图片描述
使用ucli的方式进行fsdb dump，ucli设置如下

call \$fsdbDumpfile("test.fsdb");
call \$fsdbDumpvars;
fsdbDumpSVA;
fsdbDumpon;
run;

测试代码如下

`timescale 1ns/1ps
module test();
  bit clk, rst_n, en, sigs;
  initial begin: deal_rst
    rst_n = $urandom();
    #($urandom_range(10,30));
    rst_n = 0;
    #($urandom_range(10,30));
    rst_n = 1;
  end
 
  initial begin: deal_clk
    clk = $urandom();
    forever begin:gen_clk
      #0.5;
      clk = ~clk;
    end
  end

  initial begin: deal_en
    en = $urandom();
    forever begin:gen_en
      #1;
      en = ~en;
    end
  end

  initial begin: deal_sigs
    sigs = $urandom();
    forever begin:gen_sigs
      #($urandom_range(1,3));
      sigs = ~sigs;
    end
  end

  property test(num);
    @(posedge clk) disable iff(!rst_n)
      $rose(en) |-> ##num sigs;
  endproperty
  ap_test: assert property (test(2));

  initial begin:dump_fsdb //如果使用ucli的方式，则不需要此段代码
    $fsdbDumpfile("test.fsdb");
    $fsdbDumpvars;
    $fsdbDumpSVA;
  end

endmodule

一些系统函数的使用
wire[10:0] a=18;
wire[10:0] b=$ceil(real'(a)/8.0)

always@(posedge clk or negedge rst_n) begin
  if($past(a)) begin
    ...
  end
  else if($rose(b)) begin
    ...
  end  
end

以下内容转载自：https://blog.csdn.net/Holden_Liu/article/details/89025918

property Delay;
    @(posedge clk) trigger |-> ##delay output
endproperty

##delay 只能是常量，比如##2，如果是变量编译报错。可以如下写：

property delay;
    int number;
    @(posedge clk) （trigger，number=delay) ##1 (1,number=number-1)[0*:$] ##0 (delay==0)  |->  output;
endproperty

在这里插入图片描述

这样就可以使用变量delay了。

property Repetition
    @(posedge clk) trigger |->  (output[*repetition]);
endproperty

output[*reprtition] repetition不可以是变量，否则编译报错。可以如下写：

property Repetition
   int number;
   @(posedge clk) (trigger,number=repetition) |-> ((output, number=repetition-1)[*0:$]) ##0 (repetition==0);
endproperty

以下内容转载自：https://blog.csdn.net/Holden_Liu/article/details/120117605

assertion for reset synchronous release

code

   sequence mark_time(sig,realtime t);
      @(posedge sig) (1,t=$realtime);
   endsequence

   property p_rstn_sync(en,rstn,clk);
      realtime t1,t2;
      @(posedge clk) disable iff (!en) mark_time(rstn,t1) ##0 mark_time(clk,t2) |-> if(t1!=t2) (1,$display("rstn_sync FAIL!, sync_release time:%t",t1));
   endproperty

   a_rstn_sync: assert property (p_rstn_sync(1,rstn,clk));

The property p_rstn_sync compare the realtime of (posedge clk) and (posedge rstn).

en：enable assertion
rstn： asserted reset signal
clk：asserted clock signal

Example Wave

At posedge clk, rstn synchronous release. the events of (posedge clk) and (posedge rstn) happend at the same time 30.0ns.
Report Fail. (posedge rstn) delay 10ps to (posedge clk).