文献阅读（170）Chiplet规范

tiaozhanzhe1900

已于 2022-03-26 12:12:31 修改

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分类专栏：芯片互联文章标签：硬件架构

于 2022-02-08 09:53:59 首次发布

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文章目录

ODSA
BoW

ODSA

题目：The Open Domain-Specific Architecture
时间：2020
期刊：IEEE Micro
研究机构：圣何塞州立大学/微软/Facebook/NXP/Xilinx

ODSA的目的是为chiplet建立开放的物理与逻辑D2D接口

The open domain specific architecture (ODSA) is a project within the open compute project (OCP) community that aims to establish open physical and logical D2D interfaces for chiplets.

需要解决3个挑战：

Developing an open physical and logical D2D interface
Enabling workflows with these interfaces: formats for information exchange for manufacture, test, and debug
Developing prototypes for these interfaces: the first is a platform to prototype CBP(Chiplet-based products) designs

在这里插入图片描述

BoW

题目：Chiplet Communication Link: Bunch of Wires (BoW)
时间：2020
期刊：IEEE Micro

BoW是一种开放的D2D接口，用来平衡性能与封装的复杂度，支持320Gb/s/mm到1+Tb/s/mm不同的速率
BoW的设计目标：

一组向后兼容的D2D接口
成本低廉，对于不同设计和封装复杂度可以灵活的tradeoff

Inexpensive to implement with the flexibility to tradeoff throughput per wire for design, and packaging complexity

制程从65nm到5nm的可移植性，支持不同的bump pitch和封装技术

BoW具有两种模式，BoW Basic和BoW Fast，其中

BoW Basic：最大8Gbps速率，在silicon interposer上1mm间距，在organic interposer上5mm间距
BoW Fast：最大16Gbps速率

**Interoperation With Parallel D2D Interfaces: ** 支持AIB, HBM, Open HBI

In the data plane, a BoW slice can be electrically connected with an AIB Channel with up to 18 signal wires.

如果bump pitch更小（如40mm），那么引脚密度就大，传输速率就可以小一点；如果bump pitch很大（如130mm），引脚密度低，传输速率就可以设置的大一点，这样的话传输带宽都差不多。

One observation is that nearly equivalent bandwidth density per mm of chip edge is achievable by either implementing a lower data rate BoW (5 Gb/s) at a denser 40-mm bump pitch or a higher data rate BoW (16 Gb/s) with a less-dense 130-mm bump pitch, with the latter occupying less overall silicon area.

The ODSA also has a set of activities to develop collateral to make the interface easier to use including:
a) a test chip and a packaging prototype;
b) Interface adapters to carry off-package (PCIe, CXL, CCIX) and on-die (AXI, TileLink) protocols on D2D interfaces;
c) A proposal to build a test probe card based on the reference bump pattern