验证通过, 但很可能存在问题
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena);
parameter RST_UP = 6'd1;
parameter RST_DN = 6'd2;
parameter CNT1 = 6'd3;
parameter CNT2 = 6'd4;
parameter CNT3 = 6'd5;
parameter CNT4 = 6'd6;
reg [5:0] state, next;
integer cnt;
//ff
always @(posedge clk) begin
if(reset)
state = RST_DN;
else
state = next;
end
//trans
always @(*) begin
next = RST_UP;
case(state)
RST_UP: begin
if(reset)
next = RST_DN;
else
next = RST_UP;
end
RST_DN: begin
if(reset == 0)
next = CNT1;
else
next = RST_DN;
end
CNT1: next = CNT2;
CNT2: next = RST_UP;
default: begin
next = RST_UP;
end
endcase
end
//output
always @(posedge clk) begin
if(reset)
shift_ena = 1;
else if(state == RST_UP)
shift_ena = 0;
else
shift_ena = shift_ena;
end
endmodule