fpga控制dsp6657上电启动配置

1 Verilog代码

 dspboot_config.v

`timescale 1ns / 1ps
//dsp上电启动配置
module dspboot_config (
    ///时钟和复位
    input         SYS_CLK_50MHz,
    input         SYS_RST_n,
    //DSP启动配置
    output        DSP_POR,
    output        DSP_RESETFULL,
    output        DSP_RESET,
    inout  [12:0] DSP_BOOTMODE,
    inout         DSP_LENDIAN
);


  wire sys_reset_n;
  reg [27:0] delay_counter;
  reg [1:0] counter;
  reg clk_25m;
  reg dsp_boot_en;
  reg DSP_PRO_reg;
  reg DSP_RESETFULL_reg;

  assign sys_reset_n = SYS_RST_n;
  assign DSP_RESET = SYS_RST_n;  //DSP复位接口
  assign DSP_LENDIAN = dsp_boot_en ? 1'b1 : 1'bz;  //决定DSP的大小端，1工作在小端模式，0工作在大端模式
  //assign DSP_BOOTMODE = dsp_boot_en ? 13'b0110000000000 : 13'hz;//决定DSP的启动模式
  assign DSP_BOOTMODE = dsp_boot_en ? 13'b0000000000000 : 13'hz;  //noboot模式（调试模式）
  assign DSP_POR = DSP_PRO_reg;
  assign DSP_RESETFULL = DSP_RESETFULL_reg;




  always @(posedge SYS_CLK_50MHz or negedge sys_reset_n) begin
    if (!sys_reset_n) begin
      clk_25m <= 0;
      counter <= 0;
    end else if (counter == 1) begin
      clk_25m <= ~clk_25m;  //生成25Mhz时钟
      counter <= 0;
    end else begin
      counter <= counter + 1;
    end
  end


  always @(posedge clk_25m or negedge sys_reset_n)
    if (!sys_reset_n) begin
      delay_counter <= 28'h0;
    end else if (delay_counter <= 2000000) begin
      delay_counter <= delay_counter + 28'h1;
    end else begin
      delay_counter <= delay_counter;
    end


  always @(posedge clk_25m or negedge sys_reset_n)
    if (!sys_reset_n) begin
      DSP_PRO_reg <= 1'b0;
    end else if (delay_counter == 1565500) begin
      DSP_PRO_reg <= 1'b1;
    end else begin
      DSP_PRO_reg <= DSP_PRO_reg;
    end


  always @(posedge clk_25m or negedge sys_reset_n)
    if (!sys_reset_n) begin
      DSP_RESETFULL_reg <= 1'b0;
    end else if (delay_counter == 1631000) begin
      DSP_RESETFULL_reg <= 1'b1;
    end else begin
      DSP_RESETFULL_reg <= DSP_RESETFULL_reg;
    end


  always @(posedge clk_25m or negedge sys_reset_n)
    if (!sys_reset_n) begin
      dsp_boot_en <= 1'b0;
    end else if ((delay_counter > 1620000) & (delay_counter < 1640000)) begin
      dsp_boot_en <= 1'b1;
    end else begin
      dsp_boot_en <= 1'b0;
    end

endmodule

2 引脚约束（v5）

pin.ucf 

NET "SYS_CLK_50MHz" LOC = AM16;
NET "SYS_CLK_50MHz" PERIOD = 20 ns HIGH 50 %;
NET "SYS_RST_n" LOC = AH34;

NET "DSP_POR" LOC = H9;
NET "DSP_LENDIAN" LOC = E8;
NET "DSP_RESET" LOC = AG7;
NET "DSP_RESETFULL" LOC = K7;
NET "DSP_BOOTMODE[0]" LOC = F9;
NET "DSP_BOOTMODE[1]" LOC = E9;
NET "DSP_BOOTMODE[2]" LOC = D7;
NET "DSP_BOOTMODE[3]" LOC = L5;
NET "DSP_BOOTMODE[4]" LOC = E7;
NET "DSP_BOOTMODE[5]" LOC = K4;
NET "DSP_BOOTMODE[6]" LOC = K5;
NET "DSP_BOOTMODE[7]" LOC = F6;
NET "DSP_BOOTMODE[8]" LOC = F7;
NET "DSP_BOOTMODE[9]" LOC = E5;
NET "DSP_BOOTMODE[10]" LOC = H5;
NET "DSP_BOOTMODE[11]" LOC = J5;
NET "DSP_BOOTMODE[12]" LOC = F5;