Verilog(2): Testbench

以test  Add_half作为例子，testbench 关键字initial

module t_Add_half();

wire sum, c_out;

reg a,b;

Add_half M1 (c_out, sum, a, b); //UUT (Unit Under Test)

initial begin //Time out

 #100 $finish;

end

initial begin //Stimulus patterns

#10 a=0; b=0;

#10 b=1;

#10 a=1;

#10 b=0;