检测序列011011

检测序列011011

module seqdet (
	input clk,
	input rst_n,
	input data,
	output reg en);

parameter
		idle=4'b0000,
		seq1=4'b0001,
		seq2=4'b0010,
		seq3=4'b0011,
		seq4=4'b0100,
		seq5=4'b0101,
		seq6=4'b0110;
reg [3:0] state;		

//一段式状态机
//序列不重用；（按理：序列可重用。 都可）
always@(posedge clk)
	if(!rst_n)
		begin en<=0; state<=idle; end
	else case(state)
		idle: begin if(data==0) state<=seq1; else state<=idle; en<=0; end  //en应该也可写在首
		seq1: begin if(data==1) state<=seq2; else state<=seq1; en<=0; end
		seq2: if(data==1) state<=seq3; else state<=seq1;
		seq3: if(data==0) state<=seq4; else state<=idle;
		seq4: if(data==1) state<=seq5; else state<=seq1;
		seq5: if(data==1) state<=seq6; else state<=seq1;
		seq6: begin en<=1; if(data==0) state<=seq1; else state<=idle; end
		default: begin en<=0; state<=idle; end
		endcase
				
endmodule	

测试代码（sv）

class randdata;
    rand bit data;
endclass

module tb_seqdet( );
logic clk, rst_n, data, en;
seqdet seqdet(clk, rst_n, data, en);

initial
    begin clk=0; forever #5 clk=~clk; end 

randdata rdata;//声明句柄    
initial
    begin
    rdata=new();//分配内存，实例化
    rst_n=0;
    data=0;
    #30
    rst_n=1;
    
    forever@(posedge clk)
    begin
        assert(rdata.randomize());
        data=rdata.data;
    end
    end    
endmodule