round仲裁器（优先级相同）verilog

// 优先等级一样的仲裁器
// 4 个申请
// 思路：根据上一次的grant结果，循环查找
// 

module round_arbiter(
input clk,
input rst_n,
input [3:0] req,	// 4个申请
output reg [3:0] grant );	// 4个赋值

always@(posedge clk or negedge rst_n)
if(!rst_n)
	grant<=4'b0;
else case(grant)
	4'b0000: if(req[0]) grant<=4'b0001;
			else if(req[1]) grant<=4'b0010;
			else if(req[2]) grant<=4'b0100;
			else if(req[3]) grant<=4'b1000;
			else grant<=4'b0000;
	4'b0001: if(req[1]) grant<=4'b0010;
			else if(req[2]) grant<=4'b0100;
			else if(req[3]) grant<=4'b1000;
			else if(req[0]) grant<=4'b0001;
			else grant<=4'b0000;
	4'b0010: if(req[2]) grant<=4'b0100;
			else if(req[3]) grant<=4'b1000;
			else if(req[0]) grant<=4'b0001;
			else if (req[1]) grant<=4'b0010;
			else grant<=4'b0000;
	4'b0100: if(req[3]) grant<=4'