verilog 简单module_最简单的verilog测试

command

vcs -LDFLAGS -Wl,-no-as-needed -sverilog -full64 -timescale=1ns/1ps -y $DC_HOME/dw/sim_ver +incdir+$DC_HOME/dw/sim_ver +libext+.v +define+SIM_RAM -debug_acc test_top.sv -l ./cmp.log

./simv +vcs+nostdout -l ./run.log

verdi -sverilog test_top.sv -y $DC_HOME/dw/sim_ver +incdir+$DC_HOME/dw/sim_ver +libext+.v --ssf test_top.fsdb &

test_top.sv

module test_top();

reg[11:0] a, b;

bit clk;

initial begin

forever begin

#1ns;

clk = ~clk;

end

end

wire[23:0] c;

DW02_mult_6_stage #(

.A_width('d12),

.B_width('d12)

) u_mult_inst(

.A(a),

.B(b),

.TC(1'b0),

.CLK(clk),

.PRODUCT(c)

);

initial begin

fork

while(1) begin

@(posedge clk);

a <= $urandom_range(1, 100);

b <= $urandom_range(1, 100);

end

begin

#1000ns;

$finish;

end

join

end

initial begin

$fsdbDumpfile("top.fsdb");

$fsdbDumpvars(0, "dw_top");

end

endmodule