FPGA上升沿检测的疑问

always @ (posedge clk_a or negedge rst_n)
    begin
        if (rst_n == 1'b0) 
            begin
               pules_a_r1 <= 1'b0;
               pules_a_r2 <= 1'b0;
               pules_a_r3 <= 1'b0;
            end
        else 
            begin                                   //打3拍
               pules_a_r1 <= pulse_b;
               pules_a_r2 <= pules_a_r1;
               pules_a_r3 <= pules_a_r2;
            end
    end

assign pulse_a_pos  = (~pules_a_r3) & pules_a_r2;   //上升沿检测

assign pulse_a_neg  = pules_a_r3 & (~pules_a_r2);   //下降沿检测
assign pulse_a      = pules_a_r2;

在pulse_b,pules_a_r1,pules_a_r2,pules_a_r3这几个信号中，pulse_b是最新的状态，而pules_a_r1,pules_a_r2,pules_a_r3以此存取的是pulse_b的上个状态，上上个状态，上上上个状态。

所以检测上升沿pules_a_r2 & (~pules_a_r3);中， pules_a_r3是pules_a_r3的上一个状态，上一个状态是0，此时的状态是1，所以0到1，为上升沿检测！

always @ (posedge clk_a ornegedge rst_n) beginif (rst_n == 1'b0) begin pules_a_r1 <= 1'b0; pules_a_r2 <= 1'b0; pules_a_r3 <= 1'b0; endelsebegin//打3拍 pules_a_r1 <= pulse_b; pules_a_r2 <= pules_a_r1; pules_a_r3 <= pules_a_r2; endendassign pulse_a_pos = pules_a_r2 & (~pules_a_r3); //上升沿检测assign pulse_a_neg = pules_a_r3 & (~pules_a_r2); //下降沿检测assign pulse_a = pules_a_r2;

转载于:https://www.cnblogs.com/shanchuang-119/p/10983630.html