Verilog交通灯控制模块

简介：
用Verilog编写行为模块模拟交通灯的控制时序。【注】该代码不可综合成电路网表。
代码实现：

/*----------------------------------------------
Filename: trafic_lights.v
Function: 模拟交通灯的控制时序;[本程序不可综合]
Author: Zhang Kaizhou
Date: 2019-8-6 22:20:08
-----------------------------------------------*/
`timescale 1ns/1ns
`define clock_period 100
module trafic_lights(red, amber, green);
	//端口定义
	output red, amber, green;
	reg clock, red, amber, green;
	parameter on = 1, off = 0, red_tics = 350, 
			  amber_tics = 30, green_tics = 200;
	
	//初始化
	initial
	begin
		clock = 0; red = off; amber = off; green = off;
	end
	
	//控制时序
	always
	begin
		red = on;
		light(red, red_tics);
		amber = on;
		light(amber, amber_tics);
		green = on;
		light(green, green_tics);
	end
	
	//灯亮持续时间的任务
	task light;
		//端口定义
		output color;
		input [31 : 0] tics;
		
		//控制时序
		begin
			repeat(tics) @(posedge clock);
			color &#