SystemVerilog 概念浅析之package(import& `include)

SystemVerilog中package import和`include方式的差异 --这个文章的解释更好
SystemVerilog Coding Guidelines: Package import versus include

To explain in simple terms,

1. we use import for importing a package. Using import you can select components of a package like a class or a task or “*” to import complete package.
2. we use include to physically place the code of a file while compiling. With include, you just get entire code here but cannot have part of the include file.

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SystemVerilog中的package提供了保存和共享数据、参数和方法的机制，可以在多个module、class、program和interface中重用。
package中声明的内容都属于这个package作用域（scope）。在使用这些内容时，需要先import这个package，然后通过package引用。

SystemVerilog中的package通过package和endpackage声明

package my_pkg;
  typedefenumbit [1:0] {
    RED,YELLOW, GREEN, RSVD } e_signal;
  typedefstruct {
    bit [3:0